Siliconware Precision Industries Co., Ltd.

Yi-Feng Chang

Chin-Huang Chang

Fang-Lin Tsai

Jung-Pin Huang

Chung-Lun Liu

Yi-Min Fu

Cheng-Jen Liu

Hung-Chi Chen

Lung-Yuan Wang

Yan-Heng Chen

Wei Lung Lu

Cheng Jen Liu

A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

Fabrication method of layer structure for mounting semiconductor device

An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.

Electronic package and method for fabricating the same

Layer structure for mounting semiconductor device and fabrication method thereof

A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly.

Method for fabricating multi-chip stack structure

A method for fabricating an electronic package is provided, including the steps of: providing at least a packaging structure, wherein the packaging structure has a packaging substrate having opposite first and second sides, an electronic element disposed on the first side of the packaging substrate and a plurality of conductors formed on the first side of the packaging substrate; encapsulating the packaging structure with an insulating layer, wherein the insulating layer covers the packaging substrate; and forming an RDL (Redistribution Layer) structure on the insulating layer, wherein the RDL structure is electrically connected to the conductors. Therefore, the area of the insulating layer is not required to correspond to the area of the packaging substrate, thus allowing the area of the packaging substrate to be reduced according to the practical need so as to reduce the width of the electronic package.

Electronic package and fabrication method thereof

A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty.

Multi-chip stack structure and method for fabricating the same

The is to disclose a semiconductor package featuring inclusion of light emitter(s) providing light to indicate the states of the semiconductor package as a whole and/or the chip(s) therein. The light emitter is in an original state or flashing state or emitting state according to the states of the semiconductor package as a whole and/or the chip(s). The semiconductor package includes a carrier and a shield structure in addition to the light emitter. The chip and at least part of the carrier are covered by the shield structure. The light emitter may be partially or fully covered or sealed by the shield structure. The light emitter may also be partially or fully exposed. The shield structure is such that the light provided by the light emitter sealed therein can pass therethrough to reach the outside thereof, thereby the states of the semiconductor package as a whole and/or the chip(s) can be recognized from the outside of the semiconductor package.

Growing community of inventors

Taichung, Taiwan

Yi-Feng Chang