Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Elite Semiconductor Memory Technology, Inc

Elite Semiconductor Microelectronics Technology Inc.

Wistron Corporation

Industrial Technology Research Institute

Yi-Fan Chen

Che-Chia Chang

Yu-Chieh Kuo

Shang-Jie Wu

Huicheng Chang

Yi-Jung Chen

Mei-Yi Li

Yu-Hsun Chiu

He-Yi Cheng

Chun-Yen Peng

Cheng-Po Chau

Wen-Yu Ku

Hongfa Luan

Tse-Hua Yao

Ziwei Fang

Tsan-Chun Wang

De-Wei Yu

Yee-Chia Yeo

Tung-Heng Hsieh

Hua-Tai Lin

Sen-Hong Syue

Hsiang-Lin Chen

Yu-Bey Wu

Jhun Hua Chen

Chin-Shan Hou

Yu-Lung Tung

Chi-Tien Chen

Szu-Ying Chen

Hung-Chang Hsieh

Ming-Hung Chuang

Che-Wei Tung

Tai-Jui Wang

Hao-An Chuang

Hung Chang Hsieh

Hsien-Chun Wang

Sheng-Min Yu

Hsin-Chun Huang

Chun-Hao Hsu

Tzer-Shen Lin

Wen-Ching Sun

Yu-Chin Wu

Chen-Ying Chou

Yi-Rui Chen

Yu-Zuo Lin

Yi-Shang Chen

Yu-Tao Lin

Pin-Guan Liao

Chi-Fan Chiang

Chia-Liang Sun

Hao-Hsiang Chiang

A method includes: transporting a wafer to an apparatus, the apparatus including: a first chamber configured to receive the wafer and a first gas; a second chamber surrounding the first chamber and configured to receive a second gas; a plurality of gas inlets on a chamber wall of the second chamber; and a plurality of gas vents on the chamber wall of the second chamber; heating the first chamber while keeping a gas pressure difference between the first chamber and the second chamber within a tolerance limit; and cooling the first chamber by exchanging the second gas in the second chamber while keeping the gas pressure difference within the tolerance limit.

Annealing apparatus and method of operating the same

A method of forming a semiconductor device includes forming a sacrificial gate structure over a substrate, depositing a spacer layer on the sacrificial gate structure in a conformal manner, performing a multi-step oxidation process to the spacer layer, etching the spacer layer to form gate sidewall spacers on opposite sidewalls of the sacrificial gate structure, removing the sacrificial gate structure to form a trench between the gate sidewalls spacers, and forming a metal gate structure in the trench.

Gate spacer and formation method thereof

Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

Method of forming a semiconductor device by driving hydrogen into a dielectric layer from another dielectric layer

A display device and a bezel thereof are provided. The display device includes a display panel and a bezel. The display panel has a first surface and a second surface. The first surface includes at least one pixel pad section, and the second surface includes at least one circuit pad section. The bezel includes a first surface connecting portion, a second surface connecting portion and at least one conductive wire. The edge of the display panel having the pixel pad section and the circuit pad section is accommodated between the first surface connecting portion and the second surface connecting portion. Each conductive wire has a first end and a second end. The first end is disposed on the first surface connecting portion and the second end is disposed on the second surface connecting portion. The part of the first connecting portion having the first end corresponds to the pixel pad section, and the part of the second connecting portion having the second end corresponds to the circuit pad section.

Display device and bezel thereof

Method of forming semiconductor device by driving hydrogen into a dielectric layer from another dielectric layer

A display device includes a substrate and pixels. The substrate has an intermediate region and a peripheral region. Each of the pixels includes sub-pixels. Each of the sub-pixels includes a pad group and a light emitting diode (LED) element. The pad group has a first pad and a second pad. The LED element is electrically connected to the first pad and the second pad. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. The first pads and the second pads of the pad groups of the sub-pixels of each of the standard pixels are arranged in a first direction. The peripheral pixels include a first peripheral pixel. The first pads and the second pads of the pad groups of the sub-pixels of the first peripheral pixel are arranged in a second direction, and the first direction crosses over the second direction.

Display device

A driving circuit includes a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a regulator circuit. The first transistor, the second transistor and the light-emitting element are coupled in series between a first system voltage terminal and a second system voltage terminal. A first terminal of the first transistor is coupled to the first system voltage terminal. The third transistor is electrically coupled between a gate terminal and a second terminal of the first transistor. The fourth transistor is electrically coupled between the gate terminal of the first transistor and the second system voltage terminal. A first terminal of the first capacitor is electrically coupled to the gate terminal of the first transistor. A regulator circuit is electrically coupled to a second terminal of the first capacitor.

Driving circuit

A display apparatus includes a substrate and pixels disposed on the substrate. Each of the pixels includes sub-pixels. The substrate has an intermediate region and a peripheral region, where the peripheral region is located between an edge of the substrate and the intermediate region. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. A color displayed by a sub-pixel of a standard pixel and a color displayed by a sub-pixel of a peripheral pixel are the same, and a distance between a second transistor of the sub-pixel of the standard pixel and a pad of the sub-pixel of the standard pixel is not equal to a distance between a second transistor of the sub-pixel of the peripheral pixel and a pad of the sub-pixel of the peripheral pixel.

Display apparatus

A pixel array substrate includes a base, pixel structures, first bonding pads, first wirings, and a first testing element. The pixel structures are disposed on an active area of a first surface of the base. The first bonding pads are disposed on a peripheral region of the first surface. Each of the first wirings is disposed on a corresponding first bonding pad, a first sidewall of the base, and a corresponding second bonding pad. The first testing element is disposed on the active area of the first surface and has a first testing line. The first testing line is electrically connected to at least one of the first bonding pads, and an end of the first testing line is substantially aligned with an edge of the base.

Pixel array substrate

The present disclosure relates to a driving circuit including a pulse amplitude modulation (PAM) circuit and a pulse width modulation (PWM) circuit. The PAM circuit includes a first transistor, a first capacitor, and a second transistor. The PWM circuit includes a second capacitor, a third transistor, and a fourth transistor. The first capacitor's first terminal is connected to the first transistor's gate. The second transistor's first terminal is connected to the first capacitor's first terminal, and the second transistor's second terminal is connected to the first transistor's second terminal. The third transistor's gate is connected to the second capacitor's second terminal. The fourth transistor's first terminal is connected to the third transistor's gate, the fourth transistor's second terminal is connected to the third transistor's second terminal, and the fourth transistor's gate is connected to the second transistor's gate and configured to receive a first control signal.

Driving circuit and driving method

A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.

Memory test circuit

An E-fuse circuit comprising: an E-fuse group, comprising a plurality of E-fuse sections, wherein each one of the E-fuse sections comprises a plurality of E-fuses; a multi-mode latch circuit, configured to receive an input signal to generate a first output signal in a burn in mode, and configured to receive an address to be compared to generate a second output signal in a normal mode; a first logic circuit group, configured to receive a first part of bits of the first output signal to generate a control signal in the burn in mode; and a second logic circuit group, configured to receive the control signal and a second part of bits of the first output signal to generate a selection signal in the burn in mode, to select which one of the E-fuse sections is activated.

E-fuse circuit

A display apparatus includes pixels, each of which includes first and second pixel driver circuits, first and second driver pads electrically connected to the first and second pixel driver circuits, respectively, a first LED element, first and second connection lines electrically connected to the first and second pixel driver circuits, respectively, and first and second repair pads electrically connected to the first and second connection lines, respectively. A first electrode of the first LED element is electrically connected to the first driver pad. The first repair pad, the second repair pad, the first driver pad, and the second driver pad are structurally separated. A first pixel of the pixels further includes a second LED element overlapping the first and second repair pads of the first pixel, and a first electrode of the second LED element is electrically connected to the second repair pad.

Semiconductor device having hydrogen in a dielectric layer

Growing community of inventors

Hsinchu, Taiwan

Yi-Fan Chen