Macronix International Co., Ltd.

Interface Optoelectronics (shenzhen) Co., Ltd.

General Interface Solution Limited

Interface Technology (chengdu) Co., Ltd.

Yi-Fan Chang

Su-Chueh Lo

Chun-Hsiung Hung

Kuen-Long Chang

Cheng Ming Yih

Ken-Hui Chen

Yung-Feng Lin

Ken Hui Chen

Kuen Long Chang

Kuo Yu Liao

Jian Shing Liu

Ta Kang Chu

Chu Ching Wu

Tai-Feng Chen

Chun-Yi Lee

Chun Hsiung Hung

Jian-Syu Lin

Chen-Hsing Huang

Jeng-Kuan Lin

Tsung-Ju Hu

Chi-Hsien Huang

Cheng-Ming Yi

Po-Sen Wang

A data serializer, a latch data device using the same and a controlling method thereof are provided. The data serializer includes at least one data buffer and a de-skew buffer. The data buffer at least receives an inputting data and a controlling signal. An outputting signal and a complementary outputting signal, which is complementary to the outputting signal, are formed when the controlling signal is at a predetermined level. The de-skew buffer receives the complementary outputting signal to accelerate or slow down forming the outputting signal.

Data serializer, latch data device using the same and controlling method thereof

Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.

Managing data transfers in semiconductor devices by separating circuits for lower-speed-type data and higher-speed-type data

Disclosed is a semiconductor device that has a first layer including conductive material, a bond wire coupled to an upper surface of the first layer, and a second layer including conductive material underneath the first layer. One or more interconnects couple the second layer to the first layer. In an example, the second layer has a plurality of discontinuous sections that includes (i) a connected section coupled to the one or more interconnects and (ii) one or more floating sections that are at least in part surrounded by the connected section, where the one or more floating sections are electrically floating and isolated from the connected section. The semiconductor device also includes an under-pad circuit on a substrate underneath the second layer, the under-pad circuit to transmit signals to one or more components external to the semiconductor device though the first layer.

Bond pad layout including floating conductive sections

A fixture for bonding films to an object includes a base, a cavity wall fixed to the base, and a receiving cavity defined by the cavity wall and the base. The cavity wall includes opposing inner and outer surfaces and an end surface at an end away from the base. The end surface defines protrusions interconnecting with recesses and being recessed towards the base. Each recess penetrates the inner surface and the outer surface. A method for employing the device is also provided. The fixture and the method for bonding avoid center wrapping after bonding.

Fixture for bonding purposes and method for bonding using the fixture

An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.

Configurable data integrity mode, and memory device including same

The present disclosure provides a touch device. The touch device includes a touch panel and an external circuit. The touch panel is configured to detect touch operations. The external circuit is configured to drive the touch panel. A plurality of connection structures extend from edges of the touch panel towards the external circuit. The plurality of connection structures are electrically conductive and are electrically coupled to the external circuit. The connection structures are configured to transmit touch signals from the touch panel to the external circuit.

Touch device with touch function

A decode switch and a method for controlling a decode switch are provided. The decode switch includes a power source providing a first voltage, a source capacitance coupled to the power source, and a target capacitance coupled to the power source. The power source charges the source capacitance to the first voltage. The source capacitance is connected to the target capacitance and the source capacitance charges the target capacitance to a second voltage. The power source charges the target capacitance from the second voltage to the first voltage.

Decode switch and method for controlling decode switch

A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

Device and method for improving reading speed of memory

Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.

Method and apparatus of performing an erase operation on a memory integrated circuit

Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

Growing community of inventors

Pingjhen, Taiwan

Yi-Fan Chang