Promos Technologies, Inc

Mosel Vitelic Corporation

Yi Ding

Vei-Han Chan

Barbara Haselden

Improved methods of manufacturing semiconductor devices are provided to reduce dielectric loss in isolation trenches of the devices. In one example, a method of manufacturing a semiconductor device includes forming a plurality of shallow trench isolation (STI) trenches in a substrate. A tunnel oxide layer, a first conductive layer, a gate dielectric layer, and a second conductive layer are formed above the substrate. The layers are etched to delineate a plurality of stacked gate structures. In particular, the etching may include: performing a first etch of the second conductive layer, wherein at least a portion of the second conductive layer above the STI trenches remains following the first etch; and performing a second etch of the second conductive layer, wherein the remaining portion of the second conductive layer above the STI trenches and portions of the gate dielectric layer above the STI trenches are completely removed by the second etch.

Fabrication of semiconductor device exhibiting reduced dielectric loss in isolation trenches

In a memory cell () having multiple floating gates (), the select gate () is formed before the floating gates. In some embodiments, the memory cell also has control gates () formed after the select gate. Substrate isolation regions () are formed in a semiconductor substrate (). The substrate isolation regions protrude above the substrate. Then select gate lines () are formed. Then a floating gate layer () is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric () is formed over the floating gate layer, and a control gate layer () is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (). A dielectric layer () overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate (). Each control gate () overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions () are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Nonvolatile memory cell with multiple floating gates formed after the select gate

In a nonvolatile memory, the select gates (S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines () interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an dielectric () formed over control gate lines (). Each control gate line provides control gates for one column of the memory cells. The adjacent control gate lines for the adjacent memory columns are spaced from each other. The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates () are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive gate lines for the adjacent columns are spaced from each other, and non-volatile memory structures

In a nonvolatile memory, substrate isolation regions () are formed in a semiconductor substrate (). The substrate isolation regions are dielectric regions protruding above the substrate. Then select gate lines () are formed. Then a floating gate layer () is deposited. The floating gate layer is etched until the substrate isolation regions are exposed and the floating layer is removed from over at least a portion of the select gate lines. A dielectric () is formed over the floating gate layer, and a control gate layer () is deposited. The control gate layer protrudes upward over each select gate line. These protrusions are exploited to define the control gates independently of photolithographic alignment. The floating gates are then defined independently of any photolithographic alignment other than the alignment involved in patterning the substrate isolation regions and the select gate lines. In another aspect, a nonvolatile memory cell has a conductive floating gate (). A dielectric layer () overlying the floating gate has a continuous feature that overlies the floating gate and also overlies the select gate (). The control gate () overlies the continuous feature of the dielectric layer and also overlies the floating gate but not the select gate. In another aspect, substrate isolation regions () are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Nonvolatile memories and methods of fabrication

In a nonvolatile memory cell (), the select gate transistor is formed as a buried channel transistor to increase the transistor current.

Nonvolatile memory cells with buried channel transistors

In a nonvolatile memory cell having at least two floating gates, each floating gate () has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (). The spacer can be formed from a layer () deposited after the layer () which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate () can be defined without photolithography. Other embodiments are also provided.

Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions

In a nonvolatile memory, the select gates (S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines () interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric () formed over control gates (). The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates () are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures

A widened contact area (X) of a conductive feature () is formed by means of self-alignment between an edge (E) of the conductive feature and an edge (E) of another feature (). The other feature ('first feature') is formed from a first layer, and the conductive feature is formed from a second layer overlying the first layer. The edge (E) of the conductive feature is shaped to provide a widened contact area. This shaping is achieved in a self-aligned manner by shaping the corresponding edge (E) of the first feature.

Methods of fabricating integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges

A gate dielectric () for a gate () is formed by thermal oxidation simultaneously with as a dielectric on a surface of another gate (). The dielectric thickness on the other gate is controlled by the dopant concentration in the other gate. The gates may be gates of different MOS transistors, or a select gate and a floating gate of a memory cell. Other features are also provided.

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Sunnyvale, CA, United States of America

Yi Ding