Taiwan Semiconductor Manufacturing Comp. Ltd.

Anpec Electronics Corporation

Inventec Corp.

Inventec (pudong) Technology Corporation

Macronix International Co., Ltd.

Glc Semiconductor Group (cq) Co., Ltd.

National Taiwan University

Yi-Chun Shih

Yu-Der Chih

Chia-Fu Lee

Po-Hao Lee

Yen-An Chang

Hon-Jarn Lin

Chien-Yin Liu

Ku-Feng Lin

Shih-Lien Linus Lu

Yung-Fa Lin

Shou-Yi Hsu

Meng-Wei Wu

Main-Gwo Chen

Chung-Cheng Chou

Ching-Huang Wang

Meng-Chun Shih

Kuan-Chun Chen

Hsueh-Chih Yang

Chieh-Pu Lo

Jonathan Tsung-Yung Chang

Win-San Khwa

Fong-Yuan Chang

C Y Wang

Hidehiro Fujiwara

Lin-Wei Chang

Yu-Lin Chen

Shun-Min Yeh

Yen-Huei Chen

Kuen-Long Chang

Yue-Der Chih

William Joseph Gallagher

Tien-Wei Chiang

Harry-Hak-Lay Chuang

Hsin-Liang Chen

Yen-Cheng Lin

Lung-Han Peng

Wei-Chang Zhao

Haruki Mori

Chia-Chen Lu

Way-Seen Wang

Jen-Ren Huang

Yu-Huan Lin

Yi-Chieh Chiu

Yufe Feng Lin

Yuan-Jen Lee

Jing-Qing Chan

Chien-Ye Lee

Jenn-Jou Wu

Farid Nemati

Min-Hung Chou

Shu-Mei Tsan

Yung-Chang Zhang

Chao-Ching Hsu

Cy Wang

A magnetoresistive random access memory (MRAM) device is provided. The MRAM device includes a main magnetic tunnel junction (MTJ) array comprising a plurality of memory cells configured to store memory data and a reference MTJ array comprising a plurality of reference cells having MTJ structures. The MRAM device further includes a controller operatively associated with the main MTJ array and the reference MTJ array. The controller is configured to receive a gross resistance of the reference MTJ array being related to a strength of an external magnetic field, determine whether the external magnetic field is fatal based on the received gross resistance of the reference MTJ array and a pre-determined threshold, and provide notification indicating that the memory data stored in the main MTJ array is untrustworthy if it is determined that the external magnetic field around the MRAM device is fatal.

External magnetic field detection for MRAM device

In some aspects of the present disclosure, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subgroup of FAs, wherein each FA of the first subgroup includes a first number of transistors; and a second subgroup of FAs, wherein each FA of the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subgroup receives a first input from a first one of the second subgroup of FAs and a second input from a second one of the second subgroup of FAs, and each FA provides a first output to a third one of the second subgroup of FAs and a second output to a fourth one of the second subgroup of FAs.

Low power adder tree structure

A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

MRAM reference current

A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

Memory sense amplifier trimming

A memory cell includes a memory circuit and a multiplier circuit. The multiplier circuit includes an output node configured to output the output signal, a first transistor and an initialization circuit. The first transistor is coupled to the output node and the memory circuit, and is configured to receive at least the second signal. The initialization circuit is coupled to the first transistor by the output node, and is configured to initialize the multiplier circuit in response to at least a third signal or a fourth signal. The memory circuit is configured to store a first value of a first signal of a first storage node. The multiplier circuit is coupled to the memory circuit. The multiplier circuit is configured to generate an output signal in response to the first signal and a second signal. The output signal corresponds to a product of the first signal and the second signal.

Memory cell and method of operating the same

Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Method and apparatus for defect-tolerant memory-based artificial neural network

Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.

Computing-in-memory architecture

A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.

Memory device having bitline segmented into bitline segments and related method for operating memory device

A memory device includes a plurality of magnetoresistive random-access memory (MRAM) cells including a first one-time programmable (OTP) MRAM cell. A first OTP select transistor is connected to the first OTP MRAM cell. The first OTP select transistor configured to selectively apply a breakdown current to the first OTP MRAM cell to write the first OTP MRAM cell to a breakdown state.

One time programmable (OTP) magnetoresistive random-access memory (MRAM)

A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.

Duo-level word line driver

A memory circuit includes a selection circuit, a column of memory cells, and an adder tree. The selection circuit is configured to receive input data elements, each input data element including a number of bits equal to H, and output a selected set of kth bits of the H bits of the input data elements. Each memory cell of the column of memory cells includes a first storage unit configured to store a first weight data element and a first multiplier configured to generate a first product data element based on the first weight data element and a first kth bit of the selected set of kth bits. The adder tree is configured to generate a summation data element based on each of the first product data elements.

In-memory computation circuit and method

A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.

Low-dropout voltage regulator circuit

A reference voltage generator includes an input terminal configured to receive an enable signal and an output terminal configured to provide an output signal. A voltage generator circuit is arranged to generate a first output voltage signal, and a pre-settling circuit is arranged to generate a second output voltage. The pre-settling circuit is configured to provide the second output voltage signal at the output terminal in response to the enable signal received at the input terminal, and following a first time period provide the first output voltage at the output terminal.

Reference voltage generation

A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.

Compute in memory

In some aspects of the present disclosure, a power detection system is disclosed. In some aspects, the power detection system includes a constant-transconductance (gm) reference generator circuit receiving a power supply voltage. In some embodiments, the constant-gm reference generator circuit includes a first current mirror to provide a first reference voltage and a second current mirror to provide a second reference voltage. In some embodiments, the constant-gm reference generator circuit includes a power detection circuit coupled to the first current mirror to receive the first reference voltage. In some embodiments, the power detection circuit is coupled to the second current mirror to receive the second reference voltage. In some embodiments, the power detection is operated to receive the power supply voltage. In some embodiments, the power detection circuit is operated to provide an output voltage having one of two logic states at least based on the second reference voltage and the power supply voltage.

System and method for constant transconductance based power supply detection

Growing community of inventors

Taipei, Taiwan

Yi-Chun Shih