Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Yi-Chun Lo

Wen-Jia Hsieh

Bo-Wen Hsieh

Mi-Hua Lin

Mei-Yun Wang

Fu-Kai Yang

Chia-Der Chang

Hung-Chang Hsu

Shu-Hui Cheng

Guo-Chiang Chi

Chia-Ping Lo

Tien-Chun Wang

Hsin-Hung Chen

Jen-You Chu

Jong-Pyng Chen

Yin-Ju Yang

Jung-You Chen

En Kuang Wang

Shan-Shan Lin

Rui-Xuan Dong

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Semiconductor structure with enlarged gate electrode structure and method for forming the same

A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Gate structure and method of fabricating the same

Provided is a FinFET device including a substrate having at least one fin of the FinFET device, a gate stack, a spacer, a strained layer, a composite etching stop layer, a dielectric layer and a connector. The gate stack is across the at least one fin of the FinFET device. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer. The dielectric layer is on the composite etching stop layer. The connector is over and electrically connected to the strained layer. A first upper portion of a first sidewall of the connector is in contact with the composite etching stop layer, and a second upper portion of a second sidewall of the connector is separate from the composite etching stop layer by the dielectric layer therebetween.

FinFET device and method for forming the same

A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate structure; and a protection layer between the substrate and the raised source/drain region. The protection layer is interposed between the substrate and the raised source/drain region. An atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region.

Semiconductor device and manufacturing method thereof

The filtration material includes a supporting layer, a first selective layer disposed on the supporting layer, and a second selective layer disposed on the first selective layer. The first selective layer includes a polyimide and an ionic polymer intertwined with the polyimide. In particular, the polyimide includes at least one repeat unit having a structure represented by Formula (I) wherein Ais Ais Rand Rare independently &#x2014;H, &#x2014;CF, &#x2014;OH, &#x2014;Br, &#x2014;Cl, &#x2014;F, Calkyl group, or Calkoxy group; and X and Y are independently single bond, &#x2014;O&#x2014;, &#x2014;CH&#x2014;, &#x2014;C(CH)&#x2014;, or &#x2014;NH&#x2014;.

Filtration material

Provided is a FinFET device including a substrate having at least one fin, a gate stack, a spacer, a strained layer and a composite etching stop layer. The gate stack is across the at least one fin. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer.

FinFET device and method of forming the same

A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively.

Mechanism for forming metal gate structure

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.

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Hsinchu County, Taiwan

Yi-Chun Lo