Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Parabellum Strategic Opportunities Fund LLC

Yi-Chun Lin

Kuo-Ming Wu

Jia-Rui Lee

Alexander Kalnitsky

Ruey-Hsin Liu

Chi-Chih Chen

Chi-San Wei

Shiang-Yu Chen

Chih-Wei Chang

Jian-Hsing Lee

Fu-Hsin Chen

Shen-Hong Chou

Chih-Kuang Chen

Kuo-Chih Lee

Wan-Hua Huang

Ko-Chia Kao

Yi-Shiuan Tsai

Yi-Jing Wang

Huang-De Lin

Ming Xiang Li

Chun-Wei Chiang

Jung-Hui Hsu

Sheng-Jie Chen

Meng-Jung Yang

Reuy-Hsin Liu

A process for fabricating a semiconductor structure is disclosed. The process includes: forming an isolation trench in a substrate; forming a trench fill layer to at least fill the isolation trench in the substrate, the silicon oxide trench fill layer comprising a portion in contact with the substrate below an upper surface of the substrate; exposing a sidewall of the isolation trench and without exposing a bottom of the isolation trench in the substrate; and forming a gate structure over the substrate, wherein the gate structure contacts the sidewall of the isolation trench.

Semiconductor structure and associated fabricating method

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region adjacent to the drain region; a gate electrode over the substrate and further downwardly extends into the substrate, wherein a portion of the gate electrode below a top surface of the substrate abuts the isolation region; and a source region and a drain region formed in the substrate on either side of the gate structure. An associated method for fabricating the semiconductor structure is also disclosed.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a transistor and a diode. The transistor includes a first gate region electrically coupled to a gate driver, and a first source region and a first drain region on two sides of the first gate region. The diode includes two terminals coupled between the first drain region of the transistor and a reference voltage. The transistor has a threshold voltage greater than that of the diode.

Semiconductor device

A semiconductor device of a circuit is provided. The circuit is configured to be operated under a power supply. The semiconductor device of the circuit includes a first transistor and a second transistor. The first transistor includes a first source region in a first bulk region; a first drain region defined by a well and a doped region, wherein the first source region and the doped region are separate by a distance, which is a factor which determines a breakdown voltage of the first transistor, the breakdown voltage being associated with the power supply; and a first gate. The second transistor includes a second source region in a second bulk region, the second source region electrically connected with the first source region and the first gate.

Present application provides a method of manufacturing a semiconductor structure, including forming a well, forming a gate electrode over the well, implanting a lightly doped region in a first side of the well, implanting a first drain in the lightly doped region by a first depth, implanting a second drain in the lightly doped region by a second depth, implanting a source in a second side of the well, the second side being opposite to the first side. The second depth is greater than the first depth. The gate electrode is formed to cover a part of the lightly doped region and a part of the first drain.

Power MOSFETs manufacturing method

A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a well region, a first doped region, a drain region, a source region and a gate electrode. The first doped region of a first conductivity type is located at a first side within the well region. The drain region of the first conductivity type is within the first doped region. The source region of the first conductivity type is at a second side within the well region, wherein the second side being opposite to the first side. The gate electrode is over the well region and between the source region and the drain region. A surface of the drain region and a surface of the source region define a channel and the surface of the source region directly contacts the well region.

Power MOSFETs and methods for manufacturing the same

In some embodiments, a semiconductor device includes a first transistor and a second transistor. The first transistor includes a first source region in a first bulk region having a first concentration, and a first gate. The second transistor includes a second source region in a second bulk region having a second concentration higher than the first concentration. The second source region is connected with the first source region and the first gate.

A backlight module is disclosed in the present invention. The backlight module includes a light guiding plate, a light source, a transformer and a constrainer. The transformer is disposed between the light guiding plate and the light source. The transformer is for transforming a first beam emitted from the light source into a second beam, so as to transmit the second beam to the light guiding plate, wherein a spectrum of the first beam is different from a spectrum of the second beam. The constrainer is connected to the light source for constraining a movement of the transformer. The constrainer includes a first fixing portion disposed on the light source and a second fixing portion connected to the first fixing portion, the second fixing portion being disposed on the transformer to fix the transformer relative to the light source.

Backlight module

A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on the substrate in the active area, and a gate dielectric layer disposed between the substrate and the gate electrode. The gate dielectric layer comprises a relatively-thicker high voltage (HV) dielectric portion and a relatively-thinner low voltage (LV) dielectric portion, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode.

Semiconductor device, method of fabricating the same, and patterning mask utilizied by the method

A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.

Fully isolated high-voltage MOS device

Semiconductor device, method of fabricating the same, and patterning mask utilized by the method

A semiconductor structure includes a semiconductor substrate; a first well region of a first conductivity type in the semiconductor substrate; a metal-containing layer on the first well region, wherein the metal-containing layer and the first well region form a Schottky barrier; and a first heavily doped region of the first conductivity type in the first well region, wherein the first heavily doped region is horizontally spaced apart from the metal-containing layer.

Growing community of inventors

Hsinchu, Taiwan

Yi-Chun Lin