Hon Hai Precision Industry Co., Ltd.

Hong-fu Jin Precision Industry (shenzhen) Co., Ltd.

Ye Xin Technology Consulting Co., Ltd.

Yi-Chun Kao

Hsin-Hua Lin

Po-Li Shih

Chih-Lung Lee

Kuo-Lung Fang

Wei-Chih Chang

I-Wei Wu

I-Min Lu

Hui-Chu Lin

Chin-Yueh Liao

Wu-Liu Tsai

Chang-Chun Wan

An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.

Array substrate and method for making same

An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.

Array substrate and display device and method for making the array substrate

A high-performance TFT substrate () for a flat panel display includes a substrate (), a first conductive layer () on the substrate (), a semiconductor layer () positioned on the first conductive layer (), and a second conductive layer () positioned on the semiconductor layer (). The first conductive layer () defines a gate electrode (). The second conductive layer () defines a source electrode () and a drain electrode () spaced apart from the source electrode (). The second conductive layer () includes a first layer () on the semiconductor layer () and a second layer () positioned on the first layer (). The first layer () can be made of metal oxide. The second layer () can be made of aluminum or aluminum alloy.

TFT substrate and method for making same

A thin film transistor array panel includes a first conductive layer () including a gate electrode; a channel layer () disposed over the gate; and a second conductive layer () disposed over the channel layer (). The second conductive layer () includes a multi-layered portion defining a source electrode () and a drain electrode (), which includes a first sub-layer (-), a second sub-layer (-), and a third sub-layer (-) sequentially disposed one over another. Both the third and the first sub-layers (--) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (-) is greater than that in the third sub-layer (-). The content ratio differentiation between the first and the third sub-layers (--) affects a lateral etch profile associated with a gap () generated in the second conductive layer () between the source and the drain electrodes (), where the associated gap () width in the third sub-layer (-) is wider than that in the first sub-layer (-).

Thin film transistor array panel and conducting structure

A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.

A semiconductor device comprises a multi-layered structure disposed over a substrate () and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (-) disposed over the substrate () and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (-) substantially defining a first indium to zinc content ratio; a middle sub-layer (-) disposed over the lower sub-layer (-) and comprising a metal material; an upper sub-layer (-) disposed over the middle sub-layer (-) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (-) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (-).

Thin film transistor array panel

A method for making an array substrate includes the following steps: forming a poly-silicon semiconductor layer on a substrate; forming a buffer layer on the substrate; depositing a first metal layer, and patterning the first metal layer to form gate electrodes for a driving TFT, a switch TFT, and a poly-silicon TFT; forming a first gate insulator layer; forming a second gate insulator layer; defining through holes passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer; depositing a metal oxide layer to form a first metal oxide semiconductor layer; and depositing a second metal layer to form source electrodes and drain electrodes for the driving TFT, the switch TFT, and the poly-silicon TFT.

An in-cell touch display apparatus which is proof against static electricity or the effects of its discharge includes a color filter structure, a thin film transistor (TFT) array structure with a touch electrode layer, and a ground portion. A liquid crystal layer is located between the color filter structure and the TFT array structure, a sealant is located between the color filter structure and the TFT array structure, and a protection layer is included. The protection layer directly contacts the sealant and the protection layer, the sealant, and the ground portion form a discharge path for discharging static electricity from the in-cell touch display apparatus.

In-cell touch display apparatus

A TFT substrate includes a substrate and a plurality of TFTs on the substrate. Each TFT includes a channel layer, a source electrode and a drain electrode on opposite sides of the channel layer. An ohmic contact layer is applied between the channel layer and the source electrode, and between the channel layer and the drain electrode. Both the channel layer and the ohmic contact layer are made of a metal oxide containing zinc. The channel layer has a zinc atomic percentage of less than 35%, and the ohmic contact layer has a zinc atomic percentage of more than 65%.

Thin film transistor substrate and method for making same

A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith. The drain electrode has an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith. An area of the channel layer adjacent to and not covered by one of the source electrode and the drain electrode has an electrical conductivity lower than the electrical conductivity of other area of the channel layer.

Self-aligned metal oxide thin film transistor and method of making same

A high-performance TFT substrate for a flat panel display includes a substrate, a first conductive layer on the substrate, a semiconductor layer positioned on the first conductive layer, and a second conductive layer positioned on the semiconductor layer. The first conductive layer defines a gate electrode. The second conductive layer defines a source electrode and a drain electrode spaced apart from the source electrode. The second conductive layer includes a first layer on the semiconductor layer and a second layer positioned on the first layer. The first layer can be made of metal oxide. The second layer can be made of aluminum or aluminum alloy.

A thin film transistor (TFT) includes a substrate, a TFT formed on the substrate, and a passivation layer formed on the TFT. The TFT includes a gate, a source, a drain, and a channel layer. The source and the drain are respectively located at opposite sides of the channel layer. The channel layer includes oxygen ions which are implanted into the channel layer by an oxygen implanting process performed in an environment having an air pressure greater than a standard atmospheric pressure.

Thin film transistor substrate, manufacturing method thereof, and liquid crystal display panel using same

A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.

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Yi-Chun Kao