Realtek Semiconductor Inc.

Yi-Chun Hsieh

Hsi-En Liu

Shawn Min

Chien-Tsu Yeh

Kai-An Hsieh

Yu-Ting Chung

Pei-Tse Chiang

Chih-Kai Chien

The present disclosure provides a signal converting circuit including a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert multiple input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of multiple bit configurations of the digital signal. The reference information is relevant to a change of the phase interpolator circuit due to a manufacture process variation.

Signal converting circuit and bias voltage generation circuit thereof

A signal converting circuit includes a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert a plurality of input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to a reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of a plurality of bit configurations of the digital signal, wherein the reference information is relevant to a change of the phase interpolator circuit due to a temperature variation.

Signal converting circuit

The present invention provides a receiver including a sampling circuit, a data sampling point selection circuit and a determination circuit. The sampling circuit is configured to use a clock signal to sample an input signal to generate a sampled signal, wherein a frequency of the clock signal is greater than a frequency of the input signal. The data sampling point selection circuit is configured to filter start point data to generate a filtered start point data, and to generate a data sampling point by adding an offset to the filtered start point data, wherein the start point data corresponds to a time point that a sampled value of sampled signal starts to change. The determination circuit is configured to refer to a sampled value corresponding to the data sampling point in the sampled signal to determine a logical value of a digital output signal corresponding to the input signal.

Receiver and associated signal processing method

A variable gain amplifier device includes a variable gain amplifier circuitry and a control voltage generating circuitry. The variable gain amplifier circuitry is configured to amplify input signals to generate output signals, wherein the variable gain amplifier circuitry includes a gain setting circuit that is configured to set a gain of the variable gain amplifier circuitry according to a control voltage. The control voltage generation circuitry is configured to simulate at least one circuit portion of the variable gain amplifier circuitry, in order to generate the control voltage according to the input signals and a setting voltage.

Variable gain amplifier device

An amplifier circuit is provided, which includes an input stage circuit, at least one impedance component and a current supply circuit, where the input stage circuit is coupled between at least one input terminal of the amplifier circuit and at least one output terminal of the amplifier circuit, the impedance component is coupled between a first reference voltage and the output terminal, and the current supply circuit is coupled between a second reference voltage and the output terminal. The input stage circuit is arranged to generate a signal current in response to an input signal on the input terminal, and the current supply circuit is arranged to provide at least one adjustment current. In addition, a common mode voltage level of an output signal on the output terminal is controlled by the adjustment current, to allow the amplifier circuit to perform low voltage operations.

Amplifier circuit

A communication apparatus includes an input terminal, an output terminal, and an interference reduction circuit. The interference reduction circuit is coupled between the input terminal and the output terminal. The interference reduction circuit receives a time-varying data signal. The interference reduction circuit acquires first partial data from the data signal at a first time, and generates a first level-shifted result and a second level-shifted result according to the first partial data. The interference reduction circuit is further configured to acquire second partial data from the data signal at a second time. The interference reduction circuit selects one of the first level-shifted result and the second level-shifted result as a selected result according to the second partial data, and sends the selected result to the output terminal.

Communication apparatus and communication method

The present invention provides a decision feedback equalizer including a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit generates a first set signal and a first reset signal according to an input signal, a second set signal and a second reset signal, and the first latch circuit generates a first digital signal according to the first set signal and the first reset signal. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit generates the second set signal and the second reset signal according to the input signal, the first set signal and the first reset signal, and the second latch circuit generates a second digital signal according to the second set signal and the second reset signal.

Decision feedback equalizer

A data recovery circuit includes: a first comparison circuit for comparing two analog data signals to output a first and a second comparison signals having opposite logic values when a positive clock signal stays at an active level, and for configuring the first and second comparison signals to have a same logic value when the positive clock signal stays at an inactive level; a second comparison circuit for comparing the two analog data signals to output a third and a fourth comparison signals having opposite logic values when a negative clock signal stays at the active level, and for configuring the third and fourth comparison signals to have the same logic value when the negative clock signal stays at the inactive level; and a data signal generating circuit for generating a digital data signal according to the first through fourth comparison signals.

Growing community of inventors

Miaoli County, Taiwan

Yi-Chun Hsieh