Apple Inc.

Yi Chun Chen

Farid Nemati

Alexei Elias Kosut

Gregory S Mathews

John H Kelm

Steven R Hutsell

Kevin C Wong

Kalpana Bansal

Christopher D Prest

Robert E Jeter

Brian S Tryon

James A Yurko

Todd S Mintz

Brian M Gable

Isabel Yang

Jingkui Zheng

Lijie Bao

Jeremy Li

An apparatus includes components, a distributed timebase circuit, an interface and a Time Synchronization Circuit (TSC). The timebase circuit is configured to provide local timebases in physical proximity to the components, and synchronize the local timebases to a global timebase so as to provide a consistent time measurement. The interface is configured to be coupled to one or more devices. Transmissions on the interface are logically divided into a plurality of frames. Time on the interface is defined based on a frame number identifying a particular frame. The TSC is configured to capture a first timestamp based on the frame number corresponding to a point in time on the interface, and to concurrently capture a second timestamp based on a local timebase corresponding to the point in time, wherein the first timestamp and the second timestamp correlate time on the interface to the consistent time measurement.

Universal serial bus time synchronization

The present disclosure is directed to a computing device in which memory calibrations may be modified based on an energy budget. A computing device is configured to operate using energy provided from at least one energy source. The computing device includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform a memory calibration. The computing device further includes an energy detection circuit configured to detect and indicate an amount of energy available to the computing device. The memory controller is configured to, based on the amount of energy available to the computing device and a specified energy limit, modify a resolution of the memory calibration such that the memory calibration consumes less energy than the specified energy limit.

Memory calibration in limited power scenario

Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.

Decoding status flag techniques for memory circuits

Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.

Data corruption tracking for memory reliability

An electronic device such as a wristwatch may include a conductive housing. A corrosion-resistant coating may be deposited on the conductive housing. The coating may include transition layers and an uppermost alloy layer. The transition layers may include a chromium seed layer on the conductive housing and a chromium nitride layer on the chromium seed layer. The uppermost alloy layer may include TiCrCN or other alloys and may provide the coating with desired optical reflection and absorption characteristics. The transition layers may include a minimal number of coating defects, thereby eliminating potential sites at which visible defects could form when exposed to salt water. This may allow the electronic device to exhibit a desired color and to be submerged in salt water without producing undesirable visible defects on the conductive housing structures.

Electronic devices having corrosion-resistant coatings

Growing community of inventors

San Jose, CA, United States of America

Yi Chun Chen