Macronix International Co., Ltd.

International Business Machines Corporation

Qimonda Ag

Qimonda North America Corporation

Yi-Chou Chen

Hsiang-Lan Lung

Shih-Hung Chen

Wei-Chih Chien

Erh-Kun Lai

Simone Raoux

Feng-Ming Lee

Chung H Lam

Thomas Happ

Jan Boris Philipp

Kuo-Pin Chang

Chieh-Fang Chen

Shih Hung Chen

Ruichen Liu

Rich Liu

Alejandro Gabriel Schrott

Yen-Hao Shih

Yu-Yu Lin

Geoffrey W Burr

Chih-Yuan Lu

Charles Thomas Rettner

Kuang-Yeu Hsieh

Frances Anne Houle

Ming-Hsiang Hsueh

Chia Hua Ho

Yuyu Lin

Ming-Hsiu Lee

Matthew Joseph Breitwisch

ChiaHua Ho

Hsiang Lan Lung

Sheng-Chih Lai

Yan-Ru Chen

Chieh Fang Chen

Li-Hsin Chuang

Tung-Hua Chuang

A tactile display writer unit includes a probe having a contact tip, and at least a first actuator and a second actuator coupled to the probe, whereby activation of the actuators results in a displacement of the probe tip in one or more of a z-direction and in a lateral direction having a vector in an x-y plane. Also, a display writer includes a plurality of such units supported in an x-y array. The writer units may have a third actuator coupled to the probe. Also, a tactile vision system includes such a display writer, an image processor, and an image sensor. The processor transforms RGB image information from the image sensor into hue-based information having two or more attributes; and the actuators in the tactile display writer are activated by the information attributes. Also, a method for producing a tactile color stimulus at a site on the skin of a subject includes providing a probe having a contact tip; displacing the tip at the contact site in a direction generally normal to the skin surface at the site to an extent that relates one attribute of a hue-based model of the color, and displacing the tip in at least one lateral direction generally in a plane parallel to the skin surface at the site to an extent that relates to at least one additional attribute of the color.

Color tactile vision system

A mask read only memory containing diodes and method of manufacturing the same. The mask read only memory is a high-density three dimensional array formed by stacking a plurality of diode layers and the logic '0' or '1' is defined by whether there is a dielectric layer on the diode.

Mask read only memory containing diodes and method of manufacturing the same

Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.

Low operational current phase change memory structures

A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.

Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions

A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions

A phase change memory cell with a single element phase change thin film layer; and a first electrode and a second electrode coupled to the single element phase change thin film layer. A current flows from the first electrode to the single element phase change thin film layer, and through to the second electrode. The single element phase change thin film layer includes a single element phase change material. The single element phase change thin film layer can be less than 5 nanometers thick. The temperature of crystallization of the single element phase change material can be controlled by its thickness. In one embodiment, the single element phase change thin film layer is configured to be amorphous at room temperature (25 degrees Celsius). In one embodiment, the single element phase change thin film layer is comprised of Antimony (Sb).

Phase change memory random access device using single-element phase change material

A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

Nonvolatile memory device having a transistor connected in parallel with a resistance switching device

A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance.

Resistive memory and method for controlling operations of the same

A memory cell is arranged to enhance the electrical field of the memory element. The memory cell has a metal-oxide memory element, a nonconductive element, and a conductive element. The metal-oxide memory element is in a current path between a first electrode at a first voltage and a second electrode at a second voltage. The nonconductive element is adjacent to the metal-oxide memory element.

Nonvolatile stacked nand memory

A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

Nonvolatile memory device

Phase change based memory devices and methods for operating described herein overcome the performance limitations of slow set speeds and long recovery times commonly associated with phase change memory devices, enabling high speed operation and extending their usefulness into high speed applications typically filled by DRAM and SRAM memory.

Methods for high speed reading operation of phase change memory and device employing same

Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the metal-oxide memory element. In embodiments the activating energy can be applied by applying electrical and/or thermal energy to the metal-oxide material.

Operating method of electrical pulse voltage for RRAM application

A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer; a conductive ion buffer layer between the ion-supplying layer and the memory layer, and which allows diffusion therethrough of said ions; and a second electrode electrically coupled to the ion-supplying layer. Circuitry is coupled to the device to apply bias voltages to the first and second electrodes to induce creation and destruction of conducting bridges including the first metal element in the memory layer. The ion buffer layer can improve retention of the conducting bridge by reducing the likelihood that the first metallic element will be absorbed into the ion supplying layer.

Programmable metallization cell with ion buffer layer

Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a bias arrangement to a memory cell to change the resistance state from a higher resistance state to a lower resistance state. The bias arrangement comprises a first voltage pulse and a second voltage pulse across the phase change memory element, the second voltage pulse having a voltage polarity different from that of the first voltage pulse.

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Hsinchu, Taiwan

Yi-Chou Chen