Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi Ching Ong

Kuo-Ching Huang

Kuen-Yi Chen

Yi-Hsuan Chen

Harry-Hak-Lay Chuang

Yu-Wei Ting

Wei Ting Hsieh

Fu-Hai Li

Chun-Yang Tsai

Chien Ta Huang

A switch includes a heater layer, a phase change material (PCM) layer on the heater layer, and a spreader layer formed in proximity to the PCM layer and including a central region with a first thermal conductivity and an edge region with a second thermal conductivity different than the first thermal conductivity. A method of forming a switch includes forming a heater layer, forming a phase change material (PCM) layer on the heater layer, and forming a spreader layer in proximity to the PCM layer, such that the spreader layer includes a central region with a first thermal conductivity and an edge region with a second thermal conductivity different than the first thermal conductivity.

Phase change material (PCM) switch with variably spaced spreader layer structures and methods of forming the same

Some embodiments relate to a method of forming a redistribution layer (RDL) stack of a 3D integrated circuit stack. The method comprises removing a substrate form the first side of a first die to expose a first dielectric layer. A spiral trench is formed in the first dielectric layer with one end of the spiral trench directly over a through silicon via (TSV) beneath the first dielectric layer. A first barrier layer is formed along sidewalls of the spiral trench, the first barrier layer being thermally coupled to the TSV. A first conductive wire is formed within the spiral trench, separated from the first dielectric layer by the barrier layer.

Techniques for heat dispersion in 3D integrated circuit

A semiconductor structure may be located over a substrate, and may include a parallel connection of a first component and a second component. The first component includes a series connection of a diode and a capacitor that is selected from a metal-ferroelectric-metal capacitor and a metal-antiferroelectric-metal capacitor. The second component includes a battery structure. The semiconductor structure may be used as a combination of an energy harvesting device and an energy storage structure that utilizes heat from adjacent semiconductor devices or from other heat sources.

Energy harvest and storage device for semiconductor chips and methods for forming the same

A semiconductor device includes a first capacitor having a ferroelectric film disposed between two electrodes, a second capacitor, having another dielectric film disposed between two electrodes. A first voltage is applied across the first capacitor such that the ferroelectric film is polarized, altering the effective resistance through the device. A second voltage is applied across the first capacitor, such that a leakage current transits the ferroelectric film, and accumulates along an electrode of the second capacitor, and the gate of a transistor, thereby effecting a change to the drain to source resistance of the transistor which may be measured to determine the polarization state of the ferroelectric film.

Ferroelectric tunnel junction memory devices with enhanced read window

A semiconductor device includes a ferroelectric tunnel junction (FTJ), wherein the ferroelectric tunnel junction includes a first electrode, a ferroelectric layer disposed over the first electrode, and a second electrode disposed over the ferroelectric layer. The first electrode contains nitrogen or oxygen and is characterized by a first percentage of nitrogen or oxygen. The second electrode contains nitrogen or oxygen and is characterized by a second percentage of nitrogen or oxygen. The first percentage is different from the second percentage.

Ferroelectric tunnel junctions with conductive electrodes having asymmetric nitrogen or oxygen profiles

The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.

Integrated chip with solid-state power storage device

A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

Memory device structure and manufacturing method thereof

A semiconductor structure may include semiconductor devices located on a substrate, metal interconnect structures that are located within dielectric material layers overlying the semiconductor devices and are electrically connected to the semiconductor devices, and an energy harvesting device located over the metal interconnect structures and comprising a Schottky barrier diode, a first diode electrode located on a first side of the Schottky barrier diode, and a second diode electrode connected to a second side of the Schottky barrier diode.

Growing community of inventors

Hsinchu, Taiwan

Yi Ching Ong