Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Gloval Unichip Corp.

Yi-Chieh Wang

Tsung C Whang

Chung-Han Lin

Shou-Wen Kuo

Yun Shen Chang

Shing Lee

Cheng-Kuo Wang

Kuang-Jung Peng

A cathode assembly for a physical vapor deposition (PVD) system includes a target holder and a thickness detector. The target holder is for holding a target, in which the target has a first major surface and a second major surface. The first major surface and the second major surface are respectively proximal and distal to the target holder. The thickness detector is disposed on the target holder. At least one portion of the first major surface is exposed to the thickness detector for allowing the thickness detector to detect the thickness of the target through the first major surface.

Cathode assembly, physical vapor deposition system, and method for physical vapor deposition

An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.

Method and structure for nitrogen-doped shallow-trench isolation dielectric

A method for assembling multiple integrated circuit dies into a system-in-package chip is disclosed, the method comprising: providing a plurality of integrated circuit dies; disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated circuit dies; establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections; and packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.

Assembly structure for connecting multiple dies into a system-in-package chip and the method thereof

The present invention discloses an efficient way to connect multiple integrated circuit dies using redistribution layers (RDL) for making wire connections. Antenna diodes are used to create ground paths so as to remove non-sticking pads on the RDL to ensure the integrity of the wire connections before packaging the multiple integrated circuit dies into a system-in-package (SIP) chip, thereby eliminating unnecessary yield loss in a functional test caused by the non-sticking pads. In another aspect, electrostatic discharge (ESD) protection can be provided through the antenna diodes across two different power domains by disposing a diode in one integrated circuit die for ESD protection of a terminal in another integrated circuit die.

Growing community of inventors

Taichung, Taiwan

Yi-Chieh Wang