Mediatek Corporation

Yi-Chieh Huang

Ping-Ying Wang

Yan-Bin Luo

Bo-Jiun Chen

Ke-Chung Wu

Sung-Lin Tsai

A filter includes a filter circuit, a first processing circuit, and a second processing circuit. The filter circuit receives an input signal from an input node of the filter, and converts the input signal into a voltage output. The first processing circuit provides a first control voltage to an output node of the filter according to the voltage output, wherein the first control voltage is derived from an alternating current (AC) component of the voltage output. The second processing circuit provides a second control voltage to the output node of the filter according to the voltage output, wherein the second control voltage is derived from applying DC level shift to a direct current (DC) component of the voltage output.

Filter with direct current level shift and associated phase-locked loop circuit

A clock generator has a multi-phase controllable oscillator. The multi-phase controllable oscillator includes oscillator core circuits, and has phase nodes at which clock signals with different phases are generated, respectively. Each oscillator core circuit includes a resistive component and an inverter. The resistive component is coupled between a first phase node and a second phase node of the multi-phase controllable oscillator, wherein clock signals generated at the first phase node and the second phase node have adjacent phases. The resistive components of the oscillator core circuits are cascaded in a ring configuration. The inverter receives an input feedback clock signal from one phase node of the multi-phase controllable oscillator, and generates an output feedback clock signal to the second phase node according to the input feedback clock signal.

Clock generator using resistive components to generate sub-gate delays and/or using common-mode voltage based frequency-locked loop circuit for frequency offset reduction

A control technique for an injection-locked phase-locked loop (ILPLL) includes the following steps: providing the ILPLL with a sampling clock and an injection clock for an integral path and a proportional path of the ILPLL, respectively; making a change in the power level of the injection clock to get the phase error of the integral path of the ILPLL; and controlling the phase difference between the sampling clock and the injection clock based on the phase error of the integral path of the ILPLL.

Clock generator and integrated circuit using the same and injection-locked phase-locked loop control method

A method for performing phase shift control for timing recovery in an electronic device and an associated apparatus are provided, where the method includes: generating an output signal of an oscillator, wherein a phase shift of the output signal of the oscillator is controlled by selectively combining a set of clock signals into the oscillator according to a set of digital control signals, and the set of clock signals is obtained from a clock generator, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals; and performing timing recovery and sampling on a receiver input signal of a receiver in the electronic device according to the output signal of the oscillator to reproduce data from the receiver input signal.

Method for performing phase shift control for timing recovery in an electronic device, and associated apparatus

A modulator for generating a control code in response to a frequency control word is provided. The modulator includes an adder, an accumulator, a next state generation unit, and a code generation unit. The adder generates a frequency error signal by calculating a difference between the frequency control word and the control code. The accumulator generates a phase error signal by accumulating the frequency error signal. The phase error signal includes an integer part and a fractional part. The integer part of the phase error signal is a current state signal. The next state generation unit generates a next state signal according to a characteristic probability distribution determined by the fractional part of the phase error signal. The code generation unit generates the control code in response to the current state signal and the next state signal.

Modulator, phase locked loop using the same, and method applied thereto

A digitally controlled oscillator includes a ring oscillator and a first supplementary circuit. The ring oscillator is coupled to a supply voltage and generates a signal oscillated at an oscillating frequency. The oscillating frequency is controlled by a digital code and further varies with a supply voltage drift in a first direction. The first supplementary circuit is coupled to the ring oscillator and facilitates the oscillating frequency to vary with the supply voltage drift in a second direction reverse to the first direction.

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Taichung, Taiwan

Yi-Chieh Huang