Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi-Chieh Chiu

Wen-Ting Chu

Chih-Yang Chang

Tassa Yang

Harry-Hak-Lay Chuang

Yu-Der Chih

Yi-Chun Shih

William Joseph Gallagher

Tien-Wei Chiang

Wen-Chun You

Yu-Lin Chen

Chang-Hung Chen

Chien-Ye Lee

Jian-Cheng Huang

Jenn-Jou Wu

Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction. The broken-down state corresponds to a one-time programmed state and is not susceptible to high-temperature change, even at small sizes.

One-time-programmable (OTP) implementation using magnetic junctions

A method for verifying a write operation in a memory cell (e.g., a non-volatile memory cell) that includes performing a first read operation of the memory cell to measure a first current associated with the memory cell and comparing the measured first current associated with the memory cell to a first predetermined threshold current to determine whether the write operation changed the state of the memory cell. If the measured first current associated with the memory cell indicates the write operation did change the state of the memory cell the method further includes performing a second read operation of the memory cell to measure a second current associated with the memory cell and comparing the measured second current associated with the memory cell to a second predetermined threshold current to determine whether the write operation changed the state of the memory cell to the desired state or an intermediate state.

Write algorithm for memory to reduce failure rate of write operations

A method includes applying a first voltage setting to a memory cell for a first period of time in response to a command for programming a first logical state to the memory cell, obtaining a first stored logical state of the memory cell after the applying the first voltage setting operation, and if the first stored logical state differs from the first logical state, applying a second voltage setting to the memory cell.

Memory circuit and method of programming memory circuit

A method includes applying a first voltage setting to a first node and a second node of a selected memory cell for a first predetermined period of time in response to a command for programming a first logical state to the selected memory cell. A first stored logical state of the selected memory cell is obtained after the applying the first voltage setting operation. If the first stored logical state differs from the first logical state, a second voltage setting is applied to the first node and the second node of the selected memory cell; and a first retrial is performed. The first retrial includes applying the first voltage setting to the first node and the second node of the selected memory cell for the first predetermined period of time.

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Taipei, Taiwan

Yi-Chieh Chiu