Applied Materials, Inc.

Yi-Chiau Huang

Errol Antonio C Sanchez

Xuebin Li

Schubert S Chu

Abhishek Dube

Zhiyuan Ye

Hua Chung

Maitreyee Mahajani

Chen-Ying Wu

Kartik Bhupendra Shah

Paul Brillhart

Nyi O Myo

Anzhong Chang

Balasubramanian Ramachandran

Zhepeng Cong

Kin Pong Lo

Edric Tong

Zuoming Zhu

Saurabh Chopra

Kevin Joseph Bautista

James Francis Mack

Anhthu Ngo

Wolfgang R Aderhold

Benjamin Colombeau

Yihwan Kim

Jallepally Ravi

Errol C Sanchez

Bingxi Sun Wood

Xianzhi Tao

Andy Lo

Brendan McDougall

Wei Liu

David K Carlson

Khaled Ahmed

Abhilash J Mayur

Yi Ma

Gaurav Thareja

Patricia M Liu

Sanjay S Natarajan

Shreyas Kher

Jenn-Yue Wang

John Boland

Tejal Goyani

Joseph Yudovsky

Xinyu Bao

Kevin Griffin

Jiping Li

Lori D Washington

Gregory E Menk

Adam Brand

Masato Ishii

Tushar Mandrekar

Sheng-Chin Kung

Chia Cheng Chin

Ravi Jallepally

Sathya Chary

Miao Jin

Papo Chen

Andrew C Sherman

Pierre Tomasini

A method and apparatus for processing a semiconductor substrate is described. A substrate processing apparatus is disclosed that includes a process chamber, a substrate support disposed inside the process chamber, a plurality of lamps arranged in a lamphead and positioned proximate to the substrate support, a gas source for providing a purge gas in a lateral flow path across the substrate support, and a controller that differentially adjusts power to individual lamps of the plurality of lamps based on a direction of the flow path.

Multizone lamp control and individual lamp control in a lamphead

In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.

Thermal processing susceptor

Silicon germanium (SiGe)/silicon containing superlattice structures and methods for forming the same are provided. Various embodiments utilize SiGe layers in a SiGe/Si superlattice structure, which include varying concentrations of germanium throughout the layer. For example, in some embodiments, for each SiGe layer there is a core SiGe film with a low Ge content and two thinner SiGe layers or cladding layers positioned on opposing sides of the core SiGe film with each of the SiGe cladding layers having a higher Ge content then the core SiGe film. Various embodiments provide for SiGe layers having a germanium depth profile enabling strained SiGe superlattice deposition on Si{110} substrates.

Graded superlattice structure for gate all around devices

A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

Doping techniques

Embodiments described herein relate to a method of epitaxial deposition of p-channel metal oxide semiconductor (MMOS) source/drain regions within horizontal gate all around (hGAA) device structures. Combinations of precursors are described herein, which grow of the source/drain regions on predominantly <100> surfaces with reduced or negligible growth on <110> surfaces. Therefore, growth of the source/drain regions is predominantly located on the top surface of a substrate instead of the alternating layers of the hGAA structure. The precursor combinations include a silicon containing precursor, a germanium containing precursor, and a boron containing precursor. At least one of the precursors further includes chlorine.

Anisotropic sige:b epitaxial film growth for gate all around transistor

A method of fabricating a semiconductor device includes forming an interconnect structure over a front side of a sensor substrate, thinning the sensor substrate from a back side of the sensor substrate, etching trenches into the sensor substrate, pre-cleaning an exposed surface of the sensor substrate, epitaxially growing a charge layer directly on the pre-cleaned exposed surface of the sensor substrate, and forming isolation structures within the etched trenches.

Structure and material engineering methods for optoelectronic devices signal to noise ratio enhancement

One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.

Selective methods for fabricating devices and structures

A method for the selective formation of epitaxial layers is described herein. In the method, epitaxial layers are deposited to form source and drain regions around a horizontal gate all around (hGAA structure). The method includes co-flowing a combination of chlorinated silicon containing precursors, antimony containing precursors, and n-type dopant precursors. The resulting source and drain regions are selectively grown from crystalline nanosheets or nanowires of the hGAA structure over the non-crystalline gate structure and dielectric layers. The source and drain regions are predominantly grown in a &#x3c;110&#x3e; direction.

Selective low temperature epitaxial deposition process

Methods for depositing a silicon germanium tin boron (SiGeSn:B) film on a substrate are described. The method comprises exposing a substrate to a precursor mixture comprising a boron precursor, a silicon precursor, a germanium precursor, and a tin precursor to form a boron silicon germanium tin (SiGeSn:B) film on the substrate.

Selective SIGESN:B deposition

Methods and apparatus for forming doped material layers in semiconductor devices using an integrated selective monolayer doping (SMLD) process. A concentration of dopant is deposited on a material layer using the SMLD process and the concentration of dopant is then annealed to diffuse the concentration of dopant into the material layer. The SMLD process conforms the concentration of dopant to a surface of the material layer and may be performed in a single CVD chamber. The SMLD process may also be repeated to further alter the diffusion parameters of the dopant into the material layer. The SMLD process is compatible with p-type dopant species and n-type dopant species.

Methods and apparatus for integrated selective monolayer doping

Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

Method of fabricating a semiconductor device having reduced contact resistance

The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Embodiments of the present disclosure enable formation of a source/drain contact with reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

Semiconductor device, method of making a semiconductor device, and processing system

Methods for forming films during semiconductor device fabrication by soaking a substrate in dopant are discussed herein. The dopant soak is performed in a process chamber using at least one dopant precursor for a predetermined period of time to form a dopant layer on the substrate. The process chamber is subsequently purged of the at least one dopant precursor. At least one film precursor is introduced into the process chamber after the process chamber is purged. A film is epitaxially formed on the substrate to have at least one of a target resistivity, dopant concentration, and/or thickness. Post-processing operations can include annealing or patterning the semiconductor film, or depositing additional layers thereon.

Method of growing doped group IV materials

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Fremont, CA, United States of America

Yi-Chiau Huang