Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi-Chen Huang

Hun-Jan Tao

Yi-Nien Su

Matt Yeh

Fan-Yi Hsu

Ming-Hong Hsieh

Chao-Chen Chen

Jun-Lung Huang

Hui Ouyang

Ouyang Hui

Che-Cheng Chang

Jen-Cheng Liu

Chao-Cheng Chen

Yu-Lien Huang

Jyu-Horng Shieh

Da-Yuan Lee

Weng Chang

Kuang-Yuan Hsu

Chang-Yin Chen

Po-Chi Wu

Yih-Ann Lin

Bor-Wen Chan

Ming-Jie Huang

Peng-Fu Hsu

Zhe-Hao Zhang

Baw-Ching Perng

Chun-Li Chou

Li-Chih Chao

Hui OuYang

Shin Hsien Liao

Ching-Hui Ma

Jim Cy Huang

Yin-Shen Chu

Chien-Chung Fu

Hsin-Ching Shih

Lawrance Hsu

Li-Chih Chaio

Chun-Hsiung Chen

Hong-Ming Chen

Chien Chung Fu

A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.

Performing treatment on stressors

An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.

Method for fabricating a gate structure

A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.

Modified profile gate structure for semiconductor device and methods of forming thereof

Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.

Triangular space element for semiconductor device

Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the surface of the first conductive layer. A trench structure is formed on the via structure in the dielectric without the conductive liner layer in the trench.

Via structures and trench structures and dual damascene structures

A method for forming a metal filled semiconductor feature with improved structural stability including a semiconductor wafer having an anisotropically etched opening formed through a plurality of dielectric insulating layers revealing a first etching resistant layer overlying a conductive area; a plurality of dielectric insulating layers sequentially stacked to have alternating etching rates to a preferential etching process; subjecting the anisotropically etched opening to the preferential etching process whereby the sidewalls of the anisotropically etched opening are preferentially etched to produce etched dielectric insulating layers to form roughened sidewall surfaces; anisotropically etching through the etching resistant layer to reveal the conductive area; and, filling the anisotropically etched opening with a metal to form a metal filled semiconductor feature.

Metal filled semiconductor features with improved structural stability

Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.

Via hole and trench structures and fabrication methods thereof and dual damascene structures and fabrication methods thereof

A method for fabricating dual damascene structures having improved IC performance and reduced RC delay characteristics is provided. In one embodiment, a substrate with an etch stop layer formed thereon is provided. A dielectric layer is formed on the etch stop layer and an anti-reflective coating layer is formed on the dielectric layer. A first patterned photoresist layer having a via hole pattern is formed on the anti-reflective coating layer. The via hole pattern is thereafter etched through the anti-reflective coating layer, the dielectric layer, and the etch stop layer to form a via hole. A sacrificial via fill layer is filled in the via hole. A second patterned photoresist layer having a trench pattern is formed above the sacrificial via fill layer. The trench pattern is etched into the sacrificial via fill layer, the anti-reflective coating layer, and the dielectric layer to form a trench. The sacrificial via fill layer is removed in the via hole. A conductive layer is thereafter formed in the via hole and trench.

Method of making dual damascene with via etch through

A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes COand ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.

Process for removing organic materials during formation of a metal interconnect

A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning method may be used to clean substrates after the conclusion of an etching procedure which exposes a single film between a Cu-containing conductive material and the environment. The spin speed of the DI water clean operation prevents copper corrosion due to breakdown of the film that separates the Cu-containing conductive material from the environment.

Wet cleaning method to eliminate copper corrosion

A method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process including providing a first semiconductor feature having an anisotropically etched opening including sidewalls. The first semiconductor feature further provide an overlying photoresist layer photolithographically patterned for anisotropically etching a second semiconductor feature opening overlying and encompassing the first semiconductor feature; blanket depositing a polymeric passivation layer over the overlying photoresist layer including covering at least a portion of the sidewalls including polymeric containing residues; and, removing the polymeric passivation layer including a substantial portion of the polymeric containing residues from at least a portion of the sidewalls prior to anisotropically etching the second semiconductor feature.

Method for removing polymeric residue contamination on semiconductor feature sidewalls

A wet chemical process tank, or a wet etch tank, that has improved fluid circulation and improved uniformity in the fluid concentration in the tank is disclosed. In a preferred embodiment, a tank body is provided which has a liquid dispenser positioned therein with a plurality of liquid outlets in a vertical surface of the dispenser each having a different diameter opening for compensating the different fluid pressure in the dispenser. A more uniform liquid concentration is thus achieved in the tank cavity to perform a more uniform chemical process on the plurality of wafers. The tank body is further provided with a second endwall which has a second distance from the plurality of wafers that is at least twice the first distance between a first endwall and the plurality of wafers. When the second endwall is at least 0.5 cm shorter than the first endwall, the larger second distance together with the shorter height of the second endwall induces a large volume of liquid to overflow the second endwall and to carry away any film residues or flakes, such as that of a photoresist material, from the tank cavity and thus preventing any possible redeposition of the film residues on the wafer surface and any contamination problems.

Wet chemical process tank with improved fluid circulation

A new method is provided for the creation of an opening over which the second electrode of a MIM capacitor is to be deposited. The first electrode of the MIM is created in a first layer of Fluorine doped Silicon dioxide (SiO ) Glass (FSG) . A layer of insulation comprising silicon nitride is deposited over the surface of the first electrode. A second layer of Fluorine doped Silicon dioxide (SiO ) Glass (FSG) is deposited over the surface of the layer of silicon nitride, an etch stop layer of silicon nitride is deposited over the surface of the second layer of FSG. The layers of etch stop and the second layer of FSG are patterned and etched using a dry etch, stopping on the layer-of insulation and exposing the surface of the layer of insulation. Next-and of critical importance to the invention is a step of photoresist ashing and oxidation of the surface of the layer of silicon nitride. The layer of photoresist can now be removed while concurrently, using a wet strip, the layer of silicon nitride oxidation is removed from the surface of the layer of silicon nitride. The process of creating a MIM capacitor can then proceed by creating the second electrode of the MIM capacitor.

CU second electrode process with in situ ashing and oxidation process

Growing community of inventors

Hsin-Chu, Taiwan

Yi-Chen Huang