Qualcomm Incorporated

Yi Cao

Vincent Loncke

Thomas J Richardson

Girish Varatkar

Joseph Binamira Soriaga

Shrinivas Kudekar

Shree Krishna Pandey

Zhengming Fu

James Thomas Doyle

Raghunath Kalavai

Nazanin Darbanian

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs. Accordingly, aspects of the present disclosure provide techniques for reducing delays in a processing pipeline by, in some cases, relaxing a dependency between updating bit log likelihood ratios (LLRs) and computing a posteriori LLRs.

Deeply-pipelined high-throughput LDPC decoder architecture

Various aspects described herein relate to techniques for rate matching and interleaving in wireless communications (e.g., 5G NR). In an example, a method described herein includes encoding one or more information bits to generate a first codeblock, rate matching the first codeblock to generate a second codeblock, segmenting, using bit distribution, the second codeblock into one or more sub-blocks each having a plurality of bits. The method further includes interleaving the plurality of bits on each of the one or more sub-blocks, concatenating, using bit collection, the one or more sub-blocks to generate a third codeblock in response to the interleaving, and transmitting a signal using the third codeblock.

Techniques for rate matching and interleaving in wireless communications

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to early termination techniques for low-density parity-check (LDPC) decoder architecture.

Early termination technique for LDPC decoder architecture

Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

Capacitively-coupled hybrid parallel power supply

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Parsippany, NJ, United States of America

Yi Cao