Huazhong University of Science and Technology

Montage Technology Co., Ltd.

Huawei Technologies Co., Limited

University of Electronic Science and Technology of China

Ankon Technologies Co., Ltd

International Business Machines Corporation

Sabic Global Technolgoies B.v.

Integrated Device Technology, Inc.

Other

Symantec Corporation

Yangtze Memory Technologies Co., Ltd.

Shanghai Zhaoxin Semiconductor Co., Ltd.

East China University of Science and Technology

Zhejiang Hisun Pharmaceutical Co., Ltd.

Montage Technology (shanghai) Co., Ltd.

Yi Bu Li

Xiangshui Miao

Gang Shan

Howard Chonghe Yang

Yaxiong Zhou

Yingpeng Zhong

Lei Xu

Huajun Sun

Yadong Jiang

Hao Liu

Xiaosong Du

Tianyi Yangdai

Xin Kong

Shipu Cao

Yanli Liu

Dongjie Tang

Zhaoyuan He

Xiaodi Huang

Ze Wu

Dong Qiu

Long Cheng

Ji Fu Chi

Qinghua Zhou

Wenqian Pan

Shuo Li

Shuhui Chen

Ting Wang

Yang Liu

Qi Cheng Li

Xiaobo Wang

Sheng Yan Sun

Hong Mei Zhang

Jun Liu

Qiang Li

Bo Zhang

Yong Wang

Qing Shan Zhang

Bin Liu

Hua Bai

Chengde Wu

Junfeng Zhao

Xiao Tan

Xiao Ping Guo

Hui Jiang

Tao Yu

Ming Qiao

Tao Zhang

Xinhong Wang

Yuliang Zhi

Qinghua Mao

Xiaomin Cheng

Yuhua Cheng

Keji Huang

Kai Chen

Hai Feng Wang

Xiaoyu Liu

Peng Sun

Guiyou Pu

Xiaohe Zheng

Miao Liu

Zongquan Tang

Xinliang Zhou

Peng Yan

Xiaojing Li

Stephen Tai

Zhulin Wei

Chun Yin

Fanhua Ming

Ronggang Xu

Ting Xue

Yingqiu Wu

Xiaozhong Shi

Yangming Wang

Xiao Hua Zeng

Gui Haochen

Jinming Zhou

Xuegang Huang

Yuhui He

Fei Fei

Pan Zhou

Qun Liu

Huan Yuan

Linrong He

Penglin Wu

Chunlan Lai

Jian Hui Wu

Lin Chang

Haonan Zhang

Qiangmin Wei

Hua Qing Li

Rong Wang

Yaping Wang

Tianpeng Miao

Luhua Cheng

Xiaohua Xu

Guojun Zheng

Hongyan Li

Kai Xiao

Feizhou Wang

Lin Tao

The present invention provides an image processing method, an electronic device, and a readable storage medium. The method comprises: obtaining an original image, determining whether the current original image contains a cavity; if the current original image contains a cavity, increasing the frame rate based on the original frame rate; if the current original image does not contain a cavity, maintaining the original frame rate for image capturing. The present invention can automatically adjust the frame rate according to the actual images captured by a capsule endoscope, improving the capture of intestinal images, reducing the probability of missing shots, and achieving the goal of saving power, while enhancing the efficiency of capsule endoscope usage.

Image processing method, and electronic device and readable storage medium

Aspects of the disclosure provide a method of tilting characterization. The method includes measuring a first tilting shift of structures based on a first disposition of the structures. The structures are formed in a vertical direction on a horizontal plane of a product. A second tilting shift of the structures is measured based on a second disposition of the structures. The second disposition is a horizontal flip of the first disposition. A corrected tilting shift is determined based on the first tilting shift and the second tilting shift.

Method for tilting characterization by microscopy

The present disclosure provides a method and apparatus for parsing contiguous system addresses, and an electronic device. The method for parsing contiguous system addresses comprises: acquiring system level information upon receiving contiguous system addresses; acquiring logical address ranges of objects in a first level based on the contiguous system addresses and the system level information; and when successively acquiring logical address ranges of objects in a second level, . . . , or an Nth level of the system, acquiring logical address ranges of objects in a present level based on a logical address range of a previous level and the system level information, wherein N is the number of levels, and N is an integer greater than or equal to 2, and a logical address range of an object comprises a start address and an end address of the object.

Method and apparatus for parsing contiguous system addresses, and electronic device

The application discloses a memory controller coupled between a memory module and a host controller to control access of the host controller to the memory module, the memory controller comprising: a central buffer coupled to the host controller via a command/address bus to receive a command/address signal from the host controller, wherein the central buffer is configured to determine whether the command/address signal conforms to an authority management rule and configure a buffer control command based on the determination result, so that the buffer control command indicates whether to restrict access of the host controller to the memory module; and a data buffer coupled via a data buffer command channel to the central buffer to receive the buffer control command, wherein the data buffer is configured to selectively restrict access of the host controller to the memory module based on the buffer control command; wherein the buffer control command comprises a plurality of time-sequenced fields, and the central buffer is configured to configure a second field or a field after the second field of the plurality of time-sequenced fields in the buffer control command based on the determination result.

Memory controller and method for controlling access to a memory module

Disclosed by the disclosure is a convolutional neural network on-chip learning system based on non-volatile memory, comprising: an input module, a convolutional neural network module, an output module and a weight update module. The on-chip learning of the convolutional neural network module implements the synaptic function by using the characteristic of the memristor, and the convolutional kernel value or synaptic weight value is stored in a memristor unit; the input module converts the input signal into the voltage signal; the convolutional neural network module converts the input voltage signal layer-by-layer, and transmits the result to the output module to obtain the output of the network; and the weight update module adjusts the conductance value of the memristor in the convolutional neural network module according to the result of the output module to update the network convolutional kernel value or synaptic weight value.

Convolutional neural network on-chip learning system based on non-volatile memory

The present invention provides a preparation method of a bipolar gating memristor and a bipolar gating memristor. The preparation method includes: preparing a lower electrode; depositing a resistive material layer on the lower electrode; and depositing an upper electrode on the resistive material layer by using a magnetron sputtering manner to deposit the upper electrode, controlling upper electrode metal particles to have suitable kinetic energy by controlling sputtering power, controlling a vacuum degree of a region where the upper electrode and the resistive material layer are located, such that a redox reaction occurs spontaneously between the upper electrode and the resistive material layer during the deposition of the upper electrode to form a built-in bipolar gating layer; and continuously depositing the upper electrode on the built-in bipolar gating layer.

Preparation method of bipolar gating memristor and bipolar gating memristor

The present application discloses a Hamming weight calculation method performed by an operation apparatus. The operation apparatus includes a controller and a first calculator, wherein the controller sets an initial resistance state of the first memory to a low resistance state; determines a first gate voltage of the first transistor based on first bit data in a first binary sequence, and control an on-off state of the first transistor based on the first gate voltage; controls a target resistance state of the first memory based on the on-off state of the first transistor; and determines a Hamming weight of the first bit data based on a first output current on the source of the first transistor.

Hamming weight calculation method based on operation apparatus

An active cable avoiding influence of RX power consumption, comprising: the host connection end, the device connection end and the data wire and the auxiliary wire located between them. The auxiliary wire consists of the main power wire and the auxiliary power wire, wherein, the main power wire is used for current transmission between the VBUS of the host and the device; the auxiliary wire, one end of it is located at the host connection end and connected with the main power wire, and another end at the device connection end and is used for supply power to the active component at the device connection end. The active cable disconnects an active module of the device connection end from the VBUS and also arranges the power module between the active component and the auxiliary wire.

Active cable avoiding influence of RX power consumption

The present invention discloses a control method, system, electronic device and readable storage medium for a capsule endoscope. The method includes: providing a working apparatus, comprising a capsule endoscope, and an external data recorder for cooperating with and controlling the capsule endoscope; monitoring the received ambient power by the external data recorder before wireless transmission of the capsule endoscope or during an intermittence between two transmissions, and/or monitoring the output power of the capsule endoscope by the external data recorder as data is transmitted during wireless transmission; adjusting the operating state of the working apparatus according to the ambient power and/or output power. The present invention can monitor the power during the dormant period before image interaction and/or in the process of image interaction, thus adjust the operating state of the capsule endoscope in real time, which can improve the wireless communication performance and operating time of the capsule endoscope.

Control method, control system, electronic device and readable storage medium for capsule endoscope

A memory-based CNN, includes an input module, a convolution layer circuit module, a pooling layer circuit module, an activation function module, a fully connected layer circuit module, a softmax function module and an output module, convolution kernel values or synapse weights are stored in the NOR FLASH units; the input module converts an input signal into a voltage signal required by the convolutional neural network; the convolutional layer circuit module convolves the voltage signal corresponding to the input signal with the convolution kernel values, and transmits the result to the activation function module; the activation function module activates the signal; the pooling layer circuit module performs a pooling operation on the activated signal; the fully connected layer circuit module multiplies the pooled signal with the synapse weights to achieve classification; the softmax function module normalizes the classification result into probability values as an output of the entire network.

Memory-based convolutional neural network system

An apparatus controls access to a memory module coupled to a host controller via a data bus to exchange data with the host controller. The apparatus has a configurable information memory and comprises: an access control input port via which the apparatus receives a data access command from the host controller; a control unit to identify a data access command including an access address directed to a predetermined storage region of the memory module, and generate an information processing command based at least on the access address directed to the predetermined storage region, such that the control unit can configure the information memory based on the information processing command or provide the information processing command to the memory module; and an access control output port via which the apparatus provides the information processing command to the memory module, such that the memory module outputs corresponding data information to the host controller based on the information processing command.

Apparatus and method for controlling access to memory module

Instruction cache behavior and branch prediction are used to improve the functionality of a computing device by profiling branching instructions in an instruction cache to identify likelihoods of proceeding to a plurality of targets from the branching instructions; identifying a hot path in the instruction cache based on the identified likelihoods; and rearranging the plurality of targets relative to one another and associated branching instructions so that a first branching instruction that has a higher likelihood of proceeding to a first hot target than to a first cold target and that previously flowed to the first cold target and jumped to the first hot target instead flows to the first hot target and jumps to the first cold target.

Instruction cache behavior and branch prediction

The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

Computing array based on 1T1R device, operation circuits and operating methods thereof

The present disclosure belongs to the technical field of artificial neural networks, and provides to a max pooling processor based on 1T1R memory, comprising an input module, a max pooling operation module, and an output module; the input module is configured to transmit an operating voltage according to the convolution result in the convolutional neural network; the 1T1R memory in the max pooling operation module is configured to adjust a conductance value of the RRAM according to the gate voltage of the transistor therein to achieve the max pooling operation by using the non-volatile multi-value conductance regulation characteristic of the RRAM, and store a max pooling result; and the output module is configured to read the max pooling result and output it.

Max pooling processor based on 1T1R memory

Database recovery is based on workload priorities. A database workload is divided into a plurality of workload groups. A workload group of the plurality of workload groups is selected for recovery, in which the selecting is based on a priority of the workload group. One or more recovery actions are performed for the workload group selected for recovery.

Database recovery based on workload priorities

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Beijing, China

Yi Bu Li