Agere Systems Inc.

Agere Systems Guardian Corp.

Lucent Technologies Inc.

Infineon Technologies Ag

Yhean-Sen Lai

Zhenyu Wang

Kannan Rajamani

Jinguo Yu

Jie Song

Bahman Barazesh

Jiangtao Xi

Raja Banerjea

Robert Conrad Malkemes

Cecil William Farrow

Inseop Lee

Denis Orlando

Geoffrey Lawrence Smith

An improved multi-channel receiver for satellite broadcast applications or the like. In an exemplary embodiment, a primary AGC loop controls an analog sub-receiver adapted to simultaneously receive multiple signals. Multiple digital demodulators, coupled to the sub-receiver, demodulate the multiple received signals. Multiple secondary AGC loops, one for each received signal, compensate for variations in demodulated signal strengths caused by the primary AGC loop. A feed-forward AGC compensation technique generates scalar control values for scaling the demodulated signals before the demodulated signals are processed by the secondary AGC loops. This at least partially compensates for gain variations caused by the primary AGC, reducing received signal drop-outs before the secondary AGC loops can compensate for the gain variations. Because of systemic delays in the sub-receiver and the demodulators, the scalar control values are independently timed to be coincident with the variations in the demodulated signal strengths caused by the primary AGC loop.

Multi-channel receiver with improved AGC

In one embodiment, a demodulator demodulates a multi-carrier modulated signal having two pilot tones. The demodulator calculates a first phase angle for the first pilot tone and a second phase angle for the second pilot tone based on the time-domain multi-carrier modulated signal. A timing-frequency offset estimate is calculated using the first and second phase angles. Further, a fine carrier-frequency offset estimate is calculated for each pilot tone based on the corresponding phase angle and the timing-frequency offset estimate. Each fine carrier-frequency offset estimate is combined with a coarse estimate and weighted. The weighted estimates are then combined. In further embodiments, the timing-frequency offset estimate is weighted and combined with a weighted timing-frequency offset estimate generated using a cyclic prefix. In yet further embodiments, the weighted carrier-frequency offset estimates are combined with a weighted carrier-frequency offset estimate generated using a cyclic prefix.

Timing-frequency offset and carrier-frequency offset estimations for multi-carrier modulated signals using pilot tones

An improved multi-channel receiver for satellite broadcast applications or the like. In an exemplary embodiment, the receiver has an adaptive equalizer configurable to operate with QPSK or 8PSK modulated signals. In the equalizer, a slicer table memory responsive to an 8-level quantizer (slicer) and a select signal is configured to map the output of the quantizer into QPSK or 8PSK symbol coordinates depending on whether the QPSK or the 8PSK signal is being received. The slicer table memory may be loaded with the symbol coordinates calculated from data in the 8PSK signal. A pattern matcher determines if the 8PSK or the QPSK signal is being received and asserts the select signal to configure the slicer table memory accordingly.

Demodulator with configurable adaptive equalizer

A method for extending a tracking range of a PLL includes the steps of: establishing an initial tracking window of the PLL, the tracking window having a first width associated therewith; and dynamically adjusting the tracking window of the PLL within an extended tracking range when a frequency of an input signal supplied to the PLL is outside of the tracking window, the extended tracking range having a second width associated therewith which is greater than the first width.

Phase-locked loop (PLL) having extended tracking range

An improved multi-channel receiver for satellite broadcast applications or the like. In an exemplary embodiment, an AGC loop, under the control of an AGC processor, controls the gain of an analog sub-receiver adapted to simultaneously receive multiple signals to achieve a desired AGC setpoint signal intensity from the sub-receiver. Multiple digital demodulators, coupled to the sub-receiver by an analog-to-digital converter (ADC), demodulate the multiple received signals. The AGC controller, based upon which of the received signals are being demodulated, selects the desired AGC setpoint from a table of setpoints. The AGC controller may also provide selective power control to circuitry in the receiver and select the resolution of the ADC. The controller updates the AGC loop with step values selected from a group of values by an AGC control algorithm. Different groups of step values may be used by the controller depending on whether the signals are fading or not.

An SDARS receiver includes an analog front end configured to receive a composite signal. An A/D converter is coupled to the analog front end and converts the signal to a digitized signal. A digital down converter (DDC) is coupled to the A/D converter and down converts the digitized signal to a down converted signal. A demodulator demodulates the down converted signal. The receiver includes a digital automatic gain control (DAGC) coupled to an output of the A/D converter and before the demodulator. An automatic gain controller is coupled to the DAGC for providing an automatic gain control signal.

Single path architecture with digital automatic gain control for SDARS receivers

A single-path enhanced-algorithm digital automatic gain control (SDAGC) integrated receiver is presented. The SDAGC has a front-end RF/IF reception/processing block and associated RF/IF AGC, which outputs to a single ADC. Output from the ADC is split into two TDM and one COFDM signal pathways, each with a respective DAGC. The TDM DAGCs are controlled according to TDM post-power signals, while the COFDM, DAGC is controlled according to COFDM post- and pre-power signals. An IF Gain Decision block determines the RF/IF gain based upon the respective gains of the TDM and COFDM DAGCs. A Gain Distributor block then distributes the total gain of the system across the RF/IF AGC and the various DAGCs. To save power, the COFDM pathways may be disabled if the COFDM pre-power signal falls below a threshold value.

Method and apparatus for a single-path enhanced-algorithm digital automatic gain control integrated receiver with power management and XM interference enhancement

A dual loop, clock synchronization circuit for a receiver in a communication system. The circuitry uses a first loop of a digital phase lock loop for coarse synchronization to time stamps within the received data and uses a second loop for fine synchronization of a second numerically controlled oscillator.

Method and apparatus for providing synchronization in a communication system

A coarse carrier offset adapter for determining a coarse carrier offset for application to a received satellite signal, a method of performing coarse carrier offset adjustment and a time division multiplexing (TDM) satellite receiver. In one embodiment, the adapter includes: (1) an energy estimator configured to analyze, with respect to the received satellite signal, energies in bands on either side of a baseband as displaced by a coarse carrier offset and (2) an offset adapter coupled to the energy estimator and configured to change the coarse carrier offset until the energies become substantially equal and provide the coarse carrier offset to a digital down converter for the application.

Mobile military satellite receiver architecture for accommodating wide carrier offset and method of performing coarse carrier offset adjustment

A method and apparatus for automatically controlling the gain of a digital radio receiving circuit in which a single set of analogue amplifiers is used as the front end to feed two separate digital back-end, demodulating circuits, and in which, for optimal performance, each of the two digital demodulating circuits require the front end analogue amplifiers to operate over a significantly different dynamic range. An automatic-gain-control selector selects one of two automatic-gain control signals to set the gain of the analogue amplifier. In addition, the automatic-gain-control selector sets a compensatory gain of a digital automatic gain control in the back-end circuit not selected, so that the unselected demodulating circuit has substantially the same input signal as if it had been selected. In this way, both demodulating circuits can process the input signal as if they were in control of the analogue amplifier.

Single path front end with digital AGC in SDARS system

A COFDM demodulator providing independent DQPSK symbol amplitude and phase equalization provides improved soft-symbol estimates by reducing the possibility of clipping in the differential demodulator, improving the tolerance of the differential demodulator to finite word length effects, correcting for phase drifting between adjacent subcarriers, and improving signal-to-noise ratio (SNR) calculation accuracy for maximal ratio combining applications. Separate acquisition and tracking modes for the amplitude and phase equalizers are provided that handle start-up, reacquisition, and steady-state operation of the demodulator.

Equalization in orthogonal frequency domain multiplexing

A method and apparatus for determining frame alignment in a discrete multitone transceiver by determining a rotation of the coefficients of the shortening channel impulse response for which inter symbol interference (ISI) is minimal. The ISI is determined by multiplying the average value of a transmitted discrete multitone symbol and multiplying it by the coefficients of the shortening channel impulse response in a given rotation.

Method and apparatus for frame alignment in discrete multitone transceivers

Apparatus and devices used to achieve a computationally efficient modem having a transmit path and a receive path. The apparatuses include a Farrow phase shifter for shifting the phase of signals in the transmit path, a fractionally spaced equalizer capable of equalization and signal decimation in the receive path, a primary echo sub-canceler and a post equalizer echo canceler for canceling echoes on the receive path, and a phase locked loop and add/delete register for controlling the sampling rate of a CODEC. The method includes shifting the phase of a transmit signal using a Farrow structure, equalizing and decimating a receive signal with a fractionally spaced equalizer, canceling primary echoes on the receive signal using a sub-canceler structure and canceling remaining echoes using a post equalizer echo canceler, and adjusting the sampling rate of a CODEC using a phase locked loop and an add/delete register.

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Warren, NJ, United States of America

Yhean-Sen Lai