National Semiconductor Corporation

Bay Microsystems, Inc.

Bay Microsysems, Inc.

Ygal Arbel

Robert Louis Caulk

Christoph Dominique Loeffler-Lejeune

Christopher Konrad Wolf

Himanshu A Sanghavi

Partha Srinivasan

Hemant Bheda

A two-stage switching network that takes data from an input and first switches it through a space stage into a buffer. Data from the buffer is then switched in a time-space stage to an output. Each buffer, advantageously, holds one frame of data. Further, there are two buffers such that one may be filled from the input while the other is emptied to the output, and vice-versa. A maximum amount of data may be switched in space and time regardless of its origin and destination, effecting a switching network that is capable of the widest SONET-specified bandwidth.

Switching network

A system () for decoding a data stream allocated into data packets contains a control unit (), a stream demultiplexer (), audio and video decoders (and), a memory management unit (), and audio and video input and output buffers. Upon demultiplexing and depacketizing the data packets without interrupting the control unit, the demultiplexer sends encoded audio and video data to the audio and video input buffers. Video messages dealing with video timing information and identifying where encoded video data is stored in the video input buffer are furnished by the demultiplexer for use by the control unit. Utilizing corresponding video instructions provided from the control unit, the video decoder decodes encoded video data to produce decoded video data supplied to the video output buffer. The audio decoder decodes encoded audio data to produce decoded audio data supplied to the audio output buffer. The memory management unit controls transfer of decoded audio data to and from the audio output buffer.

System and method for decoding audio/video data such as DVD or/and DVB data

A multi-stage switching network that can hitlessly reconfigure itself comprising a controller that controls each stage separately. The controller designates the paths through each stage according to the set of paths currently active. If the set of paths changes, the controller sends a new set of paths to the first stage while using the old set of paths for the second stage during a first frame. On the next frame, the controller causes both stages to use the new set of paths.

Hitless reconfiguration of a switching network

The present invention provides an audio signal processor and method of operation thereof that enables efficient digital signal processing. Fast multiply-accumulate (MAC) and vector processing capabilities are implemented in a RISC architecture giving the high speed capabilities of a digital signal processing system the speed and efficiency of a RISC processor.

Programmable RISC-DSP architecture

A novel method and apparatus for decoding a compressed audio/video signal to produce decoded audio and decoded video signals. The decoding tasks are partitioned into 'pre-processing tasks' and 'post-processing tasks.' Pre-processing tasks involve one or more non-signal processing oriented operations which do not require extensive computing resources. Pre-processing tasks are assigned to be executed by the host processor, which can perform these tasks without straining it computational resources. Pre-processing tasks include demultiplexing the compressed audio/video stream into compressed audio and compressed video streams, performing audio pre-processing on the compressed audio stream and performing video pre-processing on the compressed video stream. Post-processing tasks involve one or more signal processing oriented operations which require extensive computing resources. Pre-processing tasks are assigned to be executed by a dedicated subprocessor. Post-processing tasks include audio post-processing and video post-processing. In an embodiment, video frame tasks are also performed as part of video post-processing. Post-processing performed by the dedicated subprocessor outputs a decoded audio signal and a decoded video signal.

Audio/video subprocessor method and structure

A novel apparatus and method is disclosed to perform discrete cosine transform (DCT) coefficient reconstruction more efficiently and using less hardware resources than prior art techniques. The invention comprises a correction factor generator apparatus which computes a correction factor which is used in the DCT coefficient reconstruction process. Use of the correction factor enables DCT coefficient reconstruction to be performed using lesser computations and lesser hardware resources than prior art techniques. The apparatus and method can be used to perform DCT coefficient reconstruction for both MPEG-1 and MPEG-2 encoded video data streams.

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Belmont, CA, United States of America

Ygal Arbel