Changxin Memory Technologies, Inc.

Yexiao Yu

Zhongming Liu

Longyang Chen

Jia Fang

Shijie Bai

Zhong Kong

Xinman Cao

Junyi Zhang

Jiayun Zhang

Xianguo Zhou

Bin Zhao

A memory device and a method for manufacturing a memory device are provided. The memory device includes: a substrate, and a plurality of first capacitors embedded in the substrate; a plurality of first vertical transistors and a plurality of second vertical transistors, in which the plurality of first vertical transistors and the plurality of second vertical transistors are arranged on the substrate, and in which each of the plurality of first vertical transistors is electrically connected to a respective one of the plurality of first capacitors; and a plurality of second capacitors arranged on the plurality of first vertical transistors and the plurality of second vertical transistors, in which each of the plurality of second capacitors is electrically connected to a respective one of the plurality of second vertical transistors.

Memory device and method for manufacturing memory device

A semiconductor structure and the method for forming the same are provided. The method includes: providing a substrate including an active region; forming a word line in the substrate including a first portion and a second portion located at the end of the first portion, wherein the second portion of the word line protrudes from the first portion of the word line along the direction perpendicular to the substrate; forming a dielectric layer covering the substrate; and etching the dielectric layer and a part of the substrate to simultaneously form a first contact hole exposing the second portion of the word line and a second contact hole exposing the active region. The invention reduces the etching time and improves the etching efficiency. It avoids an excessively large etching depth of the second contact hole, thereby reducing the damage to the active region and the leakage current inside the semiconductor structure.

Semiconductor structure and method for forming same

The present application discloses a semiconductor structure and a method for fabrication. This technique improves the stability of the bit line structure. The semiconductor structure is formed in a bit line trench in a substrate, it includes: a bit line conductive layer formed in the bit line trench, and the top surface of the bit line conductive layer is higher the top surface of the substrate; a barrier layer formed at least partially between the bit line conductive layer and the inner wall of the bit line trench; and an isolation layer formed on top of the bit line conductive layer.

Method of forming a bit line structure

Provided is a semiconductor structure and a method for manufacturing the same. The method includes forming a spin on hard mask layer on a base, active areas arranged at intervals in the base, bit lines arranged at intervals and extending in a first direction on the base, each bit line electrically connected to at least one active area, and the spin on hard mask layer filled between the bit lines and covering the bit lines; removing part of the spin on hard mask layer to form first trenches arranged at intervals and extending in a second direction; forming first sacrificial layers in the first trenches; removing the spin on hard mask layer between the first sacrificial layers to form second trenches; forming first supporting layers in the second trenches; removing the first sacrificial layers and elongating the first trenches located between adjacent bit lines to the active areas.

Semiconductor structure and method for manufacturing same

A method for manufacturing a semiconductor structure includes: providing a substrate; forming a gate trench in the substrate, the gate trench including a first trench and a second trench, the second trench being located above the first trench, communicating with the first trench, and having a width greater than a width of the first trench; and forming a gate word line in the gate trench.

A method for manufacturing a semiconductor structure includes: providing a substrate, a first mask and a second mask, etching the substrate by respectively using the first mask and the second mask, so as to form first grooves and second grooves on the substrate, wherein regions, in the substrate, where the first grooves and the second grooves are located form bit line grooves; and forming a conductive layer in each of the bit line grooves.

Method for manufacturing semiconductor structure, and semiconductor structure

Embodiments provide a semiconductor structure and a fabricating method. The method includes: providing a substrate, where a plurality of active areas arranged at intervals are provided in the substrate, and the substrate is covered with an insulating layer and a barrier layer stacked sequentially; forming, in the barrier layer, a plurality of first trenches arranged at intervals and extending along a first direction and penetrating through the barrier layer; forming a filling layer in the first trenches, and forming a first mask layer on the barrier layer and the filling layer; forming, in the first mask layer, a plurality of second trenches arranged at intervals and extending along a second direction and exposing the filling layer; and removing the filling layer exposed in the second trench and the insulating layer corresponding to the filling layer to form contact holes.

Semiconductor structure and method for fabricating same

A preparation method for a semiconductor structure and a semiconductor structure are provided. Herein, the preparation method comprises: providing a structure to be processed, wherein the structure to be processed comprises a substrate, and an etching target layer, a bottom mask layer and a first mask layer stacked on the substrate; patterning the first mask layer to form a first pattern, the first pattern exposing parts of the bottom mask layer; forming spacers with vertical sidewall morphology on sidewalls of the first mask layer; removing the first mask layer; filling a gap between the spacers with a filling layer, in which a material of the spacers to a material of the filling layer has a high etching selectivity ratio; and removing the spacers.

Preparation method for semiconductor structure and same

A manufacturing method of a semiconductor structure includes: providing a base; forming multiple bit line structures on the base, where the multiple bit line structures are parallel to each other and extend in a first direction, and a trench is formed between adjacent bit line structures; forming a first conductive layer in the trench, where a void is formed in the first conductive layer; removing a part of the first conductive layer to form a first groove, where the bottom of the first groove exposes the void; forming an epitaxial layer on an inner wall of the first groove; and allowing the epitaxial layer to epitaxially grow to form an extension portion, such that the extension portion fills the void.

Manufacturing method of semiconductor structure with epitaxial layer forming extension portion

A semiconductor structure and a manufacturing method thereof are provided. The method includes following operations. A substrate including active regions and isolation regions is provided. First trench structures are formed on the substrate, the first trench structure passing through the active region and the isolation region. Bit line contact structures are formed in the first trench structures. Bit line structures are formed on the bit line contact structures, at least part of the bit line structure being positioned in the first trench structure. Bit line protection structures are formed on the bit line structures, the bit line protection structure at least covering an upper surface of the bit line structure. Capacitor contact assemblies are formed, the capacitor contact assembly including a first capacitor contact structure and a second capacitor contact structure which covers an upper surface and part of a side wall of the first capacitor contact structure.

Semiconductor structure and manufacturing method thereof

Embodiments provide a method for fabricating a memory and a memory. This method includes: providing a substrate, the substrate being internally provided with a plurality of active areas, and each of the plurality of active areas including a first contact region and a second contact region; forming a plurality of bit lines on the substrate, each of the plurality of bit lines being connected to at least one of the first contact regions; forming an isolation layer on each of the plurality of bit lines, the isolation layer covering each of the plurality of bit lines and the substrate, the isolation layer being further provided with a plurality of filling holes corresponding to the plurality of second contact regions one to one; etching the isolation layer and the substrate along the plurality of filling holes, to fill in the plurality of second contact regions.

Method for fabricating memory and memory

A method for manufacturing the mask structure includes: forming a first mask layer, a first buffer layer, a second mask layer, and a second buffer layer sequentially stacked from bottom to top; patterning the second buffer layer and the second mask layer, as to obtain a first pattern structure, the first pattern structure exposes a part of the first buffer layer; forming a first mask pattern on sidewalls of the first pattern structure; forming a carbon plasma layer as a protective layer on an exposed part of an upper surface of the first buffer layer; removing the first pattern structure; and removing a remaining protective layer.

Method for manufacturing mask structure, semiconductor structure and manufacturing method thereof

This application provides a method for manufacturing a memory and a memory thereof. The manufacturing method includes: providing a substrate, where the substrate includes a plurality of spaced active area and each of the plurality of spaced active area includes a first contact region and a second contact region; forming a plurality of spaced bit lines on the substrate, where each of the plurality of spaced bit lines is connected to at least one first contact region; forming a first isolation layer on each of the plurality of spaced bit lines, a first trench extending in a first direction between two adjacent first isolation layers of the plurality of spaced bit lines; etching a bottom along the first trench to form a second trench; and forming a plurality of conducting wires and a plurality of second isolation layers in the second trench.

Method for manufacturing a memory

A method includes the following operations for preparing a semiconductor structure, a semiconductor, and a semiconductor memory. A first dielectric layer and a first barrier layer are deposited on a substrate including an active area in sequence. A first mask including a first etching pattern is formed on the first barrier layer, and includes a groove extending in a first direction and uniformly distributed etching holes. Herein, the groove penetrates through the etching hole, and the depth of the etching hole is larger than that of the groove. Etching is performed along the first etching pattern, to remove the first barrier layer and etch the first dielectric layer to form a conductive channel.

Method for preparing semiconductor structure using a first mask comprises a groove

A method for manufacturing a memory includes: providing a substrate having a core region provided with a word line; forming a dielectric layer on the substrate, and etching the dielectric layer to form a first filling hole exposing the word line; forming a barrier layer on a hole wall of the first filling hole, where the barrier layer located in the first filling hole surrounds and forms a first intermediate hole exposing the word line; etching the word line exposed in the first intermediate hole to remove a first residue on the word line; and forming in the first intermediate hole a first wire electrically connected to the word line.

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Hefei, China

Yexiao Yu