Sony Corporation

Sony Electronics Inc

Other

Yew-Koon Tan

Shirish C Gadre

Taner E Ozcelik

Fengduo Hu

Gong-San Yu

Lin Yin

Shuichi Maeda

Agee Ozeki

Tetsuya Fukushima

The invention uses digital signal processing (DSP) techniques to synchronize an audio encoding process with a video synchronization signal. Namely, the encoder parameters of a DSP microchip are preset according to characteristics of an audio frame. A buffer temporarily stores the audio frame prior to sending it to an encoder. The buffer then transfers the frame in response to receiving a video synchronization signal in conjunction with authorization from a microprocessor. As such, the encoding sequence of the audio frame coincides with the video synchronization signal. Since the corresponding video frame is already slaved to the video synchronization signal, the audio samples are effectively processed in sequence with the video data. Prior to outputting the encoded audio frame to a multiplexor, the encoder sends a value to the microprocessor representing the difference between the end of the encoded audio frame and a second video synchronization signal. Those audio samples are ultimately discarded from the bitstream. Thus, synchronization is achieved by beginning and effectively ending the encoding processes of both the audio and video data, respectively, in sequence with a common video synchronization clock.

Start/stop audio encoder apparatus and method for synchronizing digital audio and video signals

A digital signal processor particularly adapted for decoding digital audio. The barrel shifter of the processor includes logical circuitry, so that operations involving a combination of a logical operation and a shift, can be performed in a single pass through the combined barrel shifter/logical unit, rather than requiring separate passes through the barrel shifter and ALU, which would require more instruction cycles. The address generator of the processor, includes circuitry which concatenates the most significant bits of a base address of a table to the least significant bits of an index, to thereby rapidly generate addresses of indexed locations in a table.

Digital signal processor particularly suited for decoding digital audio

A digital signal processor which supports an instruction set including both 16-bit instructions and 32-bit instructions, so that particular portions of a program requiring only 16-bit instructions may be encoded in a 16-bit mode, thus reducing the program memory needed to store these portions. The digital signal processor switches between the 16- and 32-bit modes only in response to flow control instructions such as JUMP, CALL or RETURN instructions. JUMP and CALL instructions are coded to indicate the processor mode applicable to the instructions to which the JUMP or CALL instruction goes to, so that the processor may change modes as needed when executing the JUMP or CALL instruction. When a CALL is executed the current processor mode is stored on the processor's stack, so that in response to a RETURN instruction the processor can return to this mode by retrieving the stored mode from the stack.

Digital signal processor with variable width instructions

A circuit arrangement and method utilize a distributed extensible processing architecture to allocate various DSP functions or operations between multiple processing cores disposed on an integrated circuit device. Each processing core includes one or more hardwired datapaths to provide one or more DSP operations. Moreover, each processing core includes a programmable controller that controls the operation of each hardwired datapath via a local computer program executed by the controller. Furthermore, the processing cores are coupled to one another over a communications bus to permit data to be passed between the cores and thereby permit multiple DSP operations to be performed on data supplied to the device.

Distributed extensible processing architecture for digital signal

A method and apparatus for synchronizing the playback of audio and video frames from a program source. The method associates an audio presentation time stamp ('PTS') value with an output audio frame. Selected ones of audio and video data packets include respective audio and video PTS values representing desired playback times of the respective audio and data associated therewith. The selected ones of the audio data packets further include audio frame numbers representing a number of output frames of audio to be played back between the selected ones of the audio data packets. The method comprises the steps of first storing the audio and video PTS values in respective audio and video PTS tables during an audio demultiplexing process. In addition, the audio frame numbers are stored in frame counters in association with respective PTS values during the demultiplexing process. Thereafter, the process sequentially decodes the audio and video input data to produce respective frames of audio and video which are presented to the user. With the presentation of each audio and video frame, the respective audio and video frame counters are selectively decremented. Upon detecting one of the audio frame counters having a zero value, the audio PTS value for that zero value audio frame counter is retrieved. Thereafter, the playback of the audio and video frames is selectively modified so that frames of audio and video are played back in synchronization.

Growing community of inventors

San Jose, CA, United States of America

Yew-Koon Tan