Arm Limited

Yew Keong Chong

Andy Wangkun Chen

Sriram Thyagarajan

Gus Wai-Yan Yeung

Munish Kumar

Bikas Maiti

Sony

Ayush Kulshrestha

Rajiv Kumar Sisodia

Hsin-Yu Chen

Ettore Amirante

Martin Jay Kinkade

Sanjay Mangal

Marlin Wayne Frederick, Jr

Rahul Mathur

Vivek Asthana

Kumaraswamy Ramanathan

Mouli Rajaram Chollangi

Pratik Ghanshambhai Satasia

George McNeil Lattimore

Mudit Bhargava

Bo Zheng

Fakhruddin Ali Bohra

Vikash

James Dennis Dodrill

Teresa Louise McLaurin

Frank David Frederick

Richard Slobodnik

Paul Darren Hoxey

Vianney Antoine Choserot

Ankur Goel

Hongwei Zhu

Shardendu Shekhar

Akash Bangalore Srinivasa

Wang-Kun Chen

Tom Shore

Brian Tracy Cline

Lalit Gupta

Shri Sagar Dwivedi

Xiaoqing Xu

Paul Christopher De Dood

Daniel J Albers

Ronald Paxton Preston

Yicong Li

Penaka Phani Goberu

Khushal Gelda

Nikhil Kaushik

Jacek Wiatrowski

Vincent Phillipe Schuppe

Renu Rawat

Rachit Ahuja

Jerry Chaoyuan Wang

David William Granda

Damayanti Datta

Michael Filippo

Sachin Satish Idgunji

Alex James Waugh

Edward Martin McCombs, Jr

Akshay Kumar

Vivek Nautiyal

Joel Thornton Irby

Paul Stanley Hughes

Andrew John Turner

Hemangi Umakant Gajjewar

Wendy Arnott Elsasser

Jungtae Kwon

Jean-Luc Pelloie

Anil Kumar Baratam

Satinderjit Singh

Vincent Philippe Schuppe

Arjun Singh

Shruti Aggarwal

Gary Robert Waggoner

Marlin Frederick

Nitin Jindal

Thanusree Achuthan

David Paul Clark

Neeraj Dogra

Hemant Joshi

Yanbin Jiang

Indranil Basu

Amarnath Shanmugam

Gaurang Prabhakar Narvekar

Abhishek Baradia

Kartikey Jani

Betsie Jacob

Brian Douglas Ngai Lee

Emmanuel Jean Marie Olivier Pacaud

Matthieu Domonique Henri Pauly

Sylvia Xiuhui Li

Sai Sriharsha Manapragada

Sabarish Ittamveetil

Amaranth Shyanmugam

Balaji Ravikumar

Vibin Vincent

Sreebin Sreedhar

Abhairaj Singh

Venu Anantuni

Monu Rathore

Jean-Christophe Vial

A memory instance comprises a plurality of banks of storage cells to store data values, and input/output circuitry shared between the plurality of banks for receiving write data or outputting read data. Each bank of storage cells supports a power saving mode and an operational mode. A control interface receives power control signals for controlling use of the power saving mode. Bank power control circuitry individually controls, for each of a plurality of subsets of banks of storage cells within the same memory instance, whether that subset of banks is in the power saving mode based on the power control signals. For at least one setting for the power control signals, one subset of banks is in the power saving mode while another subset of banks in the same memory instance is in the operational mode. Also disclosed is power control circuitry which selects the power mode to use for each subset of banks and generates the power control signals.

Power saving mode control for a memory instance

Various implementations described herein are related to a device including a bitcell having a bitcell layout with a first metal layer, a second metal layer and a via programming layer. The device may have a via marking layer provided in the bitcell layout for the bitcell, and the via marking layer controls optical proximity correction of the first metal layer and the second metal layer.

Masking techniques for memory applications

Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

Configurable scan chain architecture for multi-port memory

Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

Multi-port bitcell architecture

Various implementations described herein are related to a device having logic that operates in multiple voltage domains. The device may include a backside power network with rows of segmented supply rails coupled to the logic. The rows of segmented supply rails may include alternating rail breaks that define an interchanging directional supply of power to the logic in the multiple voltage domains.

Backside power supply techniques

Various implementations described herein are directed to a method for identifying pre-routed metal lines in a higher layer of a multi-layered structure. The method may recognize gaps in the pre-routed metal lines of the higher layer, and also, the method may automatically fill the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length.

Metal routing techniques

Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.

Multi-port memory architecture

According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.

Circuitry for memory address collision prevention

Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

Multi-port circuit architecture

Various implementations described herein are related to a device having a memory cell with logic that is configured to store data and passgates that are configured to access the data stored in the logic. The device may include a first number of input-output ports that are time-multiplexed with the passgates so as to increase the first number of input-output ports to a second number of input-output ports that is greater than the first number of input-output ports.

Bitcell architecture with time-multiplexed ports

Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

Wordline modulation techniques

Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.

Frontside-to-backside intermixing architecture for coupling a frontside network to a backside network

A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

Data compressor logic circuit

Various implementations described herein are directed to a device having first circuitry with wordline drivers coupled to wordlines. The device may have second circuitry with switch structures that are coupled between a first voltage and ground. The switch structures may be configured to provide a second voltage to a power connection of each wordline driver based on the first voltage.

Wordline driver architecture

Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.

Memory architecture with DC biasing

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Austin, TX, United States of America

Yew Keong Chong