Altera Corporation

Yew Fatt (Edwin) Kok

Sergey Yuryevich Shumarayev

Kar Keng Chua

Chooi Pei Lim

Teng Chow Ooi

Chuan Khye Chai

Eng Huat Lee

Joo Ming Too

A circuit includes a phase detection circuit and a phase change circuit. The phase detection circuit compares a phase of a first periodic signal to an input signal to generate a gain signal. The phase change circuit provides phase shifts to the first periodic signal in first and second directions when the gain signal has a first value. The phase change circuit increases phase shifts provided to the first periodic signal in the first direction in response to the gain signal changing from the first value to a second value. The phase change circuit provides phase shifts to the first periodic signal in the second direction when the gain signal has the second value that are smaller than the phase shifts provided to the first periodic signal in the first direction when the gain signal has the second value.

Techniques for varying phase shifts in periodic signals

Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

Clock signal networks for structured ASIC devices

Growing community of inventors

Penang, Malaysia

Yew Fatt (Edwin) Kok