Intel Corporation

Yevgeni Sabin

Efraim Rotem

Eliezer Weissmann

Nir Rosenzweig

Yoni Aizik

Doron Rajwan

Hisham Abu Salah

Esfir Natanzon

Arik Gihon

Ido Melamed

Shay Levy

Paul S Diefenbaugh

Barnes Cooper

Alexander Gendler

Nadav Shulman

Guy M Therien

Michael Mishaeli

Gal Leibovich

Niv Tokman

Nasser A Kurd

Ehud Reshef

Ahmad Yasin

Ido Ouzieli

Dong-Ho Han

Shaun M Conrad

Zhongsheng Wang

Tomer Ziv

Ana M Yepes

Tomer Levy

Hisham Abu-Salah

Christopher J Lake

John Fallin

Hem Doshi

Nimrod Angel

Yoav Ben-Raphael

Chen Ranel

Daniel D Lederman

Amit Zeevi

Michael Shusterman

Natanel Abitan

Maor Tal

Reena Patel

Vijay Degalahal

Levy Shay

Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Device, method and system for transparently changing a frequency of an interconnect fabric

A wireless communication device for communicating across a wireless communication channel includes one or more processors configured to determine whether a further device is generating a radio frequency interference at an operating frequency; transmit a request message to the further device requesting the further device vacate the operating frequency based on the determination that the further device is generating radio frequency interference; receive a response message from the further device; and generate an instruction based on the response message.

Methods and devices for dynamically avoiding radio frequency interference

In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.

Controlling power state demotion in a processor

In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

Controlling performance states of processing engines of a processor

In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

Forcing a processor into a low power state

In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.

Processor operating by selecting smaller of requested frequency and an energy performance gain (EPG) frequency

Growing community of inventors

Haifa, Israel

Yevgeni Sabin