Taiwan Semiconductor Manufacturing Comp. Ltd.

Worldwide Semiconductor Manufacturing Corporation

Worldwide Semiconductor Corporation

Yeur-Luen Tu

Chia-Shiung Tsai

Cheng-Ta Wu

Yu-Hung Cheng

Jiech-Fun Lu

Cheng-Hsien Chou

Cheng-Yuan Tsai

Chih-Yu Lai

Chih-Hui Huang

Ping-Yin Liu

Sheng-Chau Chen

Xiaomeng Chen

Yen-Chang Chu

Min-Ying Tsai

Ru-Liang Lee

Shih Pei Chou

Shih-Pei Chou

Yuan-Hung Liu

Hung-Wen Hsu

Chung-Yi Yu

Ching-Chun Wang

Shyh-Fann Ting

Wei-Li Chen

Lan-Lin Chao

Kuo-Hwa Tzeng

Shih-Chang Liu

Shu-Ting Tsai

Tsun-Kai Tsao

Kuan-Liang Liu

Hsing-Lien Lin

Chi-Hsin Lo

Chih-Ta Wu

Chine-Gie Lou

Ching-Chung Su

Chen-Fa Lu

Dun-Nian Yaung

Keng-Yu Chou

Xin-Hua Huang

Jhy-Jyi Sze

Sheng-Chan Li

Yen-Ting Chiang

Wen-I Hsu

U-Ting Chen

Jen-Cheng Liu

Alexander Kalnitsky

Chih-Ming Chen

Yu-Jen Wang

Tzu-Hsuan Hsu

Kuo-Ming Wu

Chun-Wei Chang

Yeong-Jyh Lin

Cheng-Lung Wu

Victor Y Lu

Min-Hwa Chi

Pin-Nan Tseng

Ching-Wei Tsai

Wen-Ting Chu

Hai-Dang Trinh

Hsun-Chung Kuang

Hsiao-Hui Tseng

Min-hwa Chi

Cheng-Kang Hu

Sheng-Hsiang Chuang

Wei-Cheng Hsu

Chih-Hao Wang

Min-Feng Kao

Feng-Chi Hung

Chern-Yow Hsu

Szu-Ying Chen

Chen-Jong Wang

Chii-Ming M Wu

Chun-Chieh Chuang

Yu-Lung Yeh

Feng-Jia Shiu

Po-Wei Liu

Hung-Ling Shih

Szu-Yu Wang

Chin-Wei Liang

Chen-Hao Chiang

Wen-Chin Lin

Chun-Tsung Kuo

Kuo-Chi Tu

Ming Chyi Liu

Shou-Gwo Wuu

Tien-Lu Lin

Chen-Ming Huang

Shih-Chi Fu

Shuang-Ji Tsai

Cheng-Yuan Hsu

Yi-Shin Chu

Kuan-Chieh Huang

Ching-Sen Kuo

Kuo-Yin Lin

Jen-Sheng Yang

Ko-Hsing Chang

Bor-Wen Chan

Chia-Lin Chen

Chun-Yao Chen

Gwo-Yuh Shiau

Kung Linliu

The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.

Semiconductor structure having a silicon active layer formed over a SiGe etch stop layer and an insulating layer with a through silicon via (TSV) passed therethrough

An apparatus for wafer bonding includes a transfer module and a plasma module. The transfer module is configured to transfer a semiconductor wafer. The plasma module is configured to apply a first type of plasma to perform a reduction operation upon a surface of the semiconductor wafer at a temperature within a predetermined temperature range to convert metal oxides on the surface of the semiconductor wafer to metal, and apply a second type of plasma to perform a plasma operation upon the surface of the semiconductor wafer at a room temperature outside the predetermined temperature range to activate a surface of the semiconductor wafer.

Apparatus and method for wafer bonding

Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.

Semiconductor-on-insulator wafer having a composite insulator layer

A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.

Structure for embedded gettering in a silicon on insulator wafer

Various embodiments of the present disclosure are directed towards an integrated chip including a first substrate having a front-side and a back-side opposite the front-side. A first doped region is in the first substrate and extends continuously from the front-side to the back-side. A conductive contact is over the first doped region. A conductive layer is between the first doped region and the conductive contact. The first doped region abuts a lower surface and sides of the conductive layer.

Conductive contact for ion through-substrate via

In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes introducing a first processing gas of an atomic layer deposition (ALD) process on the semiconductor substrate in a chamber; introducing a second processing gas of the ALD process on the semiconductor substrate in the chamber; creating an exhaust flow from the chamber; monitoring a concentration of the first processing gas of the ALD process in the exhaust flow; in response to the monitored concentration of the first processing gas of the ALD process in the exhaust flow, introducing a cleaning gas into the chamber.

Method of optimizing film deposition process in semiconductor fabrication by using gas sensor

The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

Back-side deep trench isolation structure for image sensor

The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a pixel region arranged between one or more trenches formed by sidewalls of the substrate. One or more dielectric materials are arranged along the sidewalls of the substrate forming the one or more trenches. A conductive material is disposed within the one or more trenches. The conductive material is electrically coupled to an interconnect disposed within a dielectric arranged on the substrate.

Image sensor scheme for optical and electrical improvement

Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

MIM capacitor with a symmetrical capacitor insulator structure

The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the etch stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.

Semiconductor structure and manufacturing method thereof

Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Method for forming a semiconductor-on-insulator (SOI) substrate

In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.

Selective polysilicon growth for deep trench polysilicon isolation structure

An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.

Image sensor having stacked metal oxide films as fixed charge film

In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer

Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

Fabrication method of metal-free SOI wafer

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Taichung, Taiwan

Yeur-Luen Tu