Sun Microsystems, Inc.

Samsung Electronics Co., Ltd.

Yet-Ping Pai

Dae Suk Jung

Seong Rai Cho

Le Trong Nguyen

Khanh M Le

Yu-Yen Mo

Manoj Gopalan

Kong-Fai Woo

Venkat R Podduturi

Ghun Kim

A method and system for inserting repeaters at different levels in a processor hierarchy involve tracing a net in a processor circuit followed by inserting repeaters at different locations in the net. The net is a circuit trace of wiring between circuit elements of a circuit, the net being divided into two nets. One net includes internal circuit elements of a processor component and another net includes external circuit elements of a processor component. A repeater solution, which includes inserted repeaters coupled to the internal circuit elements, is instantiated to other processor components. Subsequently, after instantiation of the repeater solution, repeaters are inserted in the nets external to the processor component.

Hierarchical repeater insertion

One embodiment of the present invention provides a system that facilitates routing nets between cells in a circuit layout. During operation, the system receives a circuit design to be routed, wherein the circuit design includes multiple circuit blocks that have been placed at specific locations within the circuit layout. Next, the system determines estimated lengths for nets that couple these circuit blocks together. The system then calculates the delay for the nets that couple the circuit blocks using a class one rule. If the delay in a given net is greater than a specified delay, the system inserts a virtual repeater into the given net to decrease the delay.

Method and apparatus for assigning nets to metal layers during circuit routing

One embodiment of the present invention provides a system that considers inductive effects while analyzing noise and propagation delay effect in a circuit layout. The system operates by first receiving the circuit layout, wherein the circuit layout specifies a plurality of nets that carry signals between circuit elements. Next, the system converts a given net into a single signal path, which is divided into a number of segments. The system then calculates inductance, capacitance, and resistance values for each segment. Next, the system uses these inductance, capacitance, and resistance values to produce a model for each segment. The system then couples together models for each segment into a model for the given net. The system uses the model for the given net to determine a noise and propagation delay effect through the given net.

Method and apparatus for analyzing inductive effects in a circuit layout

The present invention organizes the circuits on a VLSI chip into clusters. A number of channels exist in-between the clusters. Blocks of repeaters are used in a linear array, and are placed adjacent the edges of the clusters where repeaters are estimated to be needed. The repeater cells themselves are preferably formed to have a width less than or equal to the width of a line track for routing lines such that an array of repeater cells can be lined up with an array of routing lines in a bus.

Repeater blocks adjacent clusters of circuits

A cache control unit and a method of controlling a cache. The cache is coupled to a cache accessing device. A first cache request is received from the device. A request identification information is assigned to the first cache request and provided to the requesting device. The first cache request may begin to be processed. A second cache request is received from the cache accessing device. The second cache request is assigned to the first cache request and provided to the requesting device. The first and second cache requests are finally fully serviced.

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Milpitas, CA, United States of America

Yet-Ping Pai