Integrated Device Technology, Inc.

Performance Semiconductor Corporation

Fairchild Camera and Instrument Corp.

Yeshayahu Mor

Philip A Bourekas

Scott Revak

Leonardo Sandman

Avigdor Willenz

Yeshayahu Schatzberger

Dan Wilnai

Nabil G Damouny

Allan M Schiffman

Min-Siu Huang

Danh LeNgoc

A structure and a method are provided to implement a reset scheme for an integrated circuit supporting a variety of testing and debugging equipment. The control and I/O pins of the integrated circuit are each set to a high impedance state when the signals of a reset pin and a mode pin are both asserted. If the signal on the mode pin remains asserted at the time the signal on the reset pin is negated, the control and I/O pins of the integrated circuit remain in the high impedance state until the next time the signal on the reset pin is asserted. Otherwise, the control and I/O pins of the integrated circuits are enabled upon negation of the signal on the reset pin. In one embodiment, the mode pin is multiplexed with an pin used for receiving interrupt signals during functional operation.

Flexible reset scheme supporting normal system operation, test and

A structure and a method are provided for refilling a block of memory words stored in a cache memory. The structure and method provide a read buffer to optimally match the processor speed with the main memory using read clock enable RdCEn and acknowledge (Ack) signals. The RdCEn signal is provided as each memory word is available from the main memory. The Ack signal is provided to indicate the time at which the processor may empty the read buffer at the processor clock rate without subsequently executing a wait cycle to wait for any remaining memory words in the block to arrive. The benefit of the present invention is obtained without incurring a performance penalty on the single word read operation.

Structure and method for multiple-level read buffer supporting optimal

A structure and a method for directing execution of instructions are provided in a microprocessor with an on-chip cache memory. In one embodiment, the microprocessor provides a debug mode, which is activated by a signal on a mode pin. In the debug mode, when a signal is received on a second mode pin indicating that an instruction is to be provided on the memory bus is desired, a cache miss is generated at the next instruction fetch. Thus, the processor is forced to fetch the next instruction from main memory. The instruction is then provided on the memory bus as though it is fetched from the main memory in response to the read cycle resulting from the cache miss.

Hardware control structure and method for off-chip monitoring entries of

In a microprocessor, two output pins are dedicated to providing information to assist in diagnosing problems relating to internal instruction and data caches or the software executing in the caches. The information on the pins is time-multiplexed. In a first phase, the pins indicate whether the data or instruction cache is accessed and whether a cache miss has occurred. In a second phase, the pins carry signals identifying the address reference which resulted in a cache miss.

Multiplexed status and diagnostic pins in a microprocessor with on-chip

A multiplexed address and data bus system provides a minimum pin count with byte enable and burst address counter support. The partitioning of the address bus includes separate byte enables to indicate specifically which bytes of the word are being accessed, and two independent address lines which can function as a counter to support the burst refill. Both block reads or single datum transfers are handled similarly: a single addressing phase with multiple data phases; and all addresses in the memory system; are derived directly from the same pins regardless of whether it is a block read or not. The system allows for low cost packaging while maintaining a variety of system capabilities.

Minimum pin-count multiplexed address/data bus with byte enable and

A structure and a method are provided to bring internal signals of an integrated circuit to the external pins for monitoring purpose. In one embodiment, the signals on an internal bus between an on-chip cache and a CPU in a microprocessor are provided on the microprocessor's pins for a bidirectional data/address bus, when the bidirectional data/address bus is not used for data/address bus transactions with the main memory or the peripheral input/output devices. In this embodiment, reserved pins are used to selectively enable the address/data bus for bringing out the signals of the on-chip bus.

Structure and method for monitoring an internal cache

Normalization and scaling operations are performed by the use of the fast shifter of a micrprocessor operating in response to the system clock, rather than in response to microinstructions. By local control of the fast shifter, multiple shift steps essential to normalization and scaling operations are performed at a much faster rate than possible in the prior art wherein each bit shift must be controlled by a single microinstruction, and without the heavy cost in integrated circuit chip area that a barrel shifter requires. When a scaling or normalization operation is to be performed, the system clock is gated to the fast shifter, thus allowing the shift operation to take place in response to the gated clock. Simultaneously, when the shifting operation is taking place, a WAIT signal is provided, telling the microprocessor to postpone action on the next microinstruction until the shifter operation has been completed. The fast shifter is capable of performing either single or double bit shifts to either the right or left, as desired. The fast shifter is also use to implement the parametric shift instructions in the microprocessor instruction set, providing a similar performance enhancement to these operations.

Fast shifter method and structure

A microprocessor for processing operand bits has a 16 bit primary arithmetic logic unit (ALU) and shifter and a 24 bit auxiliary ALU and shifter operating in conjunction with the primary ALU. Some of the total number of operand bits are loaded into the auxiliary ALU and processed therein in advance of the processing of bits in the primary ALU. This permits a 16 bit microprocessor to perform operations with 32 bit or 48 bit operands without any performance penalties and without requiring an increase in the microcode utilized. The invention is particularly useful and valuable in such operations as multiplication and division operations, that are of a highly repetitive nature, and for all floating point operations.

Microprocessor system with extended arithmetic logic unit

Comparison of two floating point numbers is performed using a unique algorithm, which in one embodiment is implemented very efficiently in hardware, resulting in a very significant improvement in the floating point comparison execution time. In order to perform a floating point comparison, the exponents of the two numbers to be compared are subtracted. In many cases, the exponents are not equal, and simply determining which exponent is larger, combined with the signs of the mantissas of each of the floating point numbers being compared, is sufficient to determine which of the two floating point numbers being compared is larger. Alternatively, if the exponents of the two floating point numbers being compared are equal, the mantissas may be subtracted without need for shifting mantissas in order to equalize the exponents. In this manner, the floating point comparison operation is greatly simplified and the time consuming multiple shift operation is avoided, thereby vastly reducing the amount of time required to perform the floating point comparison, and thereby increasing the overall speed of operation of the microprocessor.

Method and structure for performing floating point comparison

A computer is sped up by reducing significantly the time necessary for the computer to detect and respond to an overflow following an ALU operation of a type which generates an overflow. This is done by assuring the next instruction in sequence is the one to be executed and in parallel detecting the occurrence of an overflow as the result of an implementation of a selected instruction and then producing a flag in response to the overflow. The flag is detected, and selected portions of the computer are disabled to inhibit any change in state within the computer following the generation of the overflow. An interrrupt sequence is then implemented to correct the output of the instruction which generated the overflow to compensate for the overflow. The next following instruction is then implemented after completion of the interrupt routine. Consequently, a delay following each instruction of a type which can generate an overflow is avoided unless an overflow condition actually exists because should an overflow not exist the computer automatically implements the next correct following instruction. In an alternative embodiment, an ALU operation capable of producing a branch signal is followed by the most likely microinstruction to occur. Should, however, the ALU operation indicate a branch, selected components of the computer are disabled to inhibit any change in state within the computer following the generation of the branch signal. An alternative microinstruction is then implemented in response to the branch signal. A selected sequence of microinstructions is then implemented following the completion of the alternative microinstruction. Consequently, a delay following each instruction of a type which can generate a branch is avoided unless a branch signal actually is generated.

On-line overflow response system and ALU branching structure

A microcoded data processing system utilizes common microcode execution routines for both register-to-register operations and memory-to-register operations. The system includes a memory data register for storing an operand for use in a memory-to-register operation, a pair of address registers for containing the addresses of the registers to be involved in the execution of register-to-register instructions, and circuitry responsive to generation of an instruction indicating a memory-to-register operation for generating the address of the memory data register from one of the address registers, whereby the register-to-register operations and the memory-to-register operations can share common execution routines without any performance time penalty or any increase in required microcode. The system also provides for the simultaneous generation of the addresses of all registers to be employed in instructions involving multipart operands.

Register addressing system for efficient microroutine sharing and

A modified Booth algorithm is implemented in the arithmetic logic of the ALU data path to cut the number of cycles to do a multiply in half thereby improving execution time of the multiplication operation. A Booth Encoder examines the two least significant bits of the multiplier stored in the Q2 register and the bit which was previously shifted out on the last partial product shift cycle. Based upon the status of these three bits, the Booth Encoder causes the ALU to add or substract one times the multiplicand to the contents of the partial product register and shift twice, add or substract two times the multiplicand to the contents of the partial product register and shift twice, or do nothing but shift twice. A pre ALU B shifter provides a single left shift of the multiplicand to provide the multiplication by two when same is necessary.

Microprocessor having multiplication circuitry implementing a modified

A microprocessor with a multiplexer having its output coupled to the input of the instruction register for storing instructions to be executed and applying the bits of the instruction as the input signals to a mapping PLA. The inputs of the multiplexer are the information bus coupled to external pins to receive instructions either from external memory or from an external console, and the output of the ALU. The path from the output of the ALU to the input of the instruction register allows better self testing of the processor by iteself and self-generation of input/output instructions. This structure simplifies the processor by allowing console requests, instructions from memory and self generated instructions all to be stored in the same register, i.e., the instruction register, thereby eliminating the need for separate registers for each type of instruction. Further, this structure simplifies programming of repetitive I/O instructions for polling large numbers of I/O devices having sequential addresses in memory mapped I/O applications. That is, the microprocessor has the capability of generating its own I/O instructions from an operand coming in from memory such as by adding it to the contents of an index register and supplying the result to the instruction register through the ALU output, the ALU bus, and the multiplexer as the address of the particular I/O device to read from or write to.

Microprocessor with compact mapped programmable logic array

A microprocessor comprising: an address data path; an arithmetic logic unit data path, said data paths being capable of simultaneous operation; an information bus; a shared bus register; a shared input multiplexing apparatus for selectively transferring address and data information from said information bus and data information from said arithmetic logic unit data path to said shared bus register; and a multiplexing apparatus for transferring information from said shared bus register to said arithmetic logic unit data path and to said information bus via said address data path whereby said shared bus register is selectively useable as a memory data register, a memory address register and a temporary or 'scratch-pad' register during normal operation of the microprocessor; and further comprising; a programmable logic array containing a sequence of microinstructions and apparatus connected thereto for testing the operability of the microprocessor.

High performance microprocessor system

A microprocessor for facilitating the execution of instructions which require repetitive shift and arithmetic logic unit operations comprises an arithmetic logic unit having a first and a second input and an output, a plurality of registers, at least one of which is a bidirectionally shifting register and multiplexing apparatus for selectively coupling each of said plurality of registers to said first and said second inputs and said output of said arithmetic logic unit.

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Cupertino, CA, United States of America

Yeshayahu Mor