Chartered Semiconductor Manufacturing Ltd (corporation)

Lumileds LLC

Lumileds Singapore Pte. Ltd.

Yeow Meng Teo

Wee-Hong Ng

Lap Chan

Chee Chung James Wong

Pei-Chee Mah

Geok Joo Soh

Yu-Chen Shen

Erik William Young

Madhusudan Mukhopadhyay

Zhan Hong Cen

Wali Zhang

Chee Yin Foo

Che-Chia Wei

Rajan Rajgopal

Say Gut Piew

Dong Xiang Qi

Heng Jee Kiat

Ronald Dickinson

Kah S Seah

A metal stack of layers contacting an N-type layer of a light emitting diode (LED) device comprises: an ohmic contact layer electrically contacting the N-type layer and having a work function value that is less than or equal to a work function value of the N-type layer; a reflective layer electrically contacting the ohmic contact layer; a first material barrier layer electrically contacting the reflective layer; a current carrying layer electrically contacting the first material barrier layer; and a second material barrier layer electrically contacting the current carrying layer. LED devices incorporate the metal stack of layer as a bonding material and/or as an ohmic contact-reflective material. Methods of making and using the metal stacks and LED devices are also provided.

Light emitting diode devices with bonding and/or ohmic contact-reflective material

A micro-light emitting diode (uLED) device comprises: a mesa comprising: a plurality of semiconductor layers including an n-type layer, an active layer, and a p-type layer; a p-contact layer contacting the p-type layer; a cathode contacting the first sidewall of the n-type layer; a first region of dielectric material that insulates the p-contact layer, the active layer, and a first sidewall of the p-type layer from the cathode; an anode contacting the top surface of the p-contact layer; and a second region of dielectric material that insulates the active layer, a second sidewall of the p-type layer, and the second sidewall of the n-type layer from the anode. The top surface of the p-contact layer has a different planar orientation compared to the first and second sidewalls of the n-type layer. Methods of making and using the uLED devices are also provided.

Methods of making flip chip micro light emitting diodes

Flip chip micro light emitting diodes

Described are light emitting diode (LED) devices comprising a plurality of mesas defining pixels, each of the mesas comprising semiconductor layers, an N-contact material in a space between each of the plurality of mesas, a dielectric material which insulates sidewalls of the P-type layer and the active region from the metal. A hard mask layer is above the semiconductor layers, the hard mask layer having a plurality of openings therein, each partially filled with a liner layer and partially filled with a P-metal material plug, the P-metal material plug having a width; and a passivation film is on the hard mask layer, the passivation film having a plurality of passivation film openings therein defining a width, the width of each passivation film opening being less than the width of a combination of the P-metal material plug and the liner layer.

Light emitting diode devices with defined hard mask opening

A method is provided for manufacturing an integrated circuit including a substrate with a gate layer and a gate dielectric provided on the substrate. The gate layer is formed into a gate using a process that imposes a charge in the gate dielectric. The substrate, gate, and gate dielectric are irradiated to discharge the charge across the gate dielectric.

Method using ultraviolet radiation for integrated circuit manufacturing

A method for fabricating a self-aligned antifuse cell is described. An antifuse is provided overlying a metal plug in an insulating layer on a semiconductor substrate. A dielectric layer is deposited overlying the antifuse. The dielectric layer is etched to form dielectric spacers on the sidewalls of the antifuse. A top metal layer is deposited overlying the antifuse and dielectric spacers and patterned to complete the antifuse cell in an integrated circuit device.

Method of forming top metal contact to antifuse

A new method is provided for the creation of a salicided polysilicon capacitor. A salicided layer of polysilicon is created as the lower plate of a salicided polysilicon capacitor over the surface of a field isolation region. A layer of silicon nitride is deposited over the field oxide isolation region including the surface of the salicided polysilicon layer. A layer of TEOS is deposited over the surface of the layer of silicon nitride, a layer if titanium nitride is deposited over the surface of the layer of TEOS. The layer of TiN is etched after which the layer of TEOS is etched. The etch of the layer of TEOS is an overetch whereby TEOS is symmetrically removed from underneath the etched layer of TiN, leaving remnants of TEOS in place underneath the etched layer of TiN while at the same time creating air gaps underneath the etched layer of TiN. A layer of silane based oxide is deposited over the surface of the field oxide isolation region including the surface of the etched layer of TiN, thus enclosing the air gaps that have been created underneath the etched layer of TiN. The latter layer of silane based oxide is patterned and etched, forming the upper plate of the salicided polysilicon capacitor. The TEOS remnants remaining in place underneath the etched layer of TiN is part of the dielectric layer of the capacitor.

Method of forming salicided poly to metal capacitor

A method is described for overcoming the non-conformity and poor step coverage incurred when materials such as metals and barrier materials are deposited into contact or via openings by physical-vapor-deposition (PVD) techniques such as sputtering and evaporation. Conventional PVD deposition into a vertical walled opening results in the formations of cusps along the walls at the mouth of the opening. These cusps obstruct the material stream into the depth of the opening, resulting in inadequate coverage at the base of the opening particularly at the corners. This increases the chance of failure of the barrier material resulting in a reliability exposure. In addition, the cusps, if not removed, cause the formation of voids in subsequently deposited conductive plugs. The invention teaches the insulative layer, wherein the openings are formed, to be deposited to a greater thickness than required by the design. The openings are then formed and filled with a spin-on-glass. The insulative layer is then polished to the design thickness, removing the cusps. The spin-on-glass, which protects the openings from damage and contamination during polishing, is removed and an adhesion layer is applied prior to the deposition of the conductive material of the contact or via.

Method for forming contacts and vias with improved barrier metal

An improved and new method for forming stacked polysilicon contacts for use in multilevel conducting interconnection wiring in semiconductor integrated circuits has been developed. The polysilicon contacts are self-aligned between wiring levels and the fabrication process results in a substantially planar top insulating layer surface.

Method for forming stacked polysilicon

A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer. Finally, the filled isotropically etched aperture is planarized until there is exposed a flange of the first polysilicon layer formed into the ledge.

Stacked container capacitor using chemical mechanical polishing

A method for producing an interconnect on a semiconductor device has silicon containing conductive surfaces and dielectric surfaces. The process includes forming separate regions of a blanket first refractory metal silicide on the silicon containing conductive surfaces, the first refractory metal silicide being composed of a first refractory metal and silicon from the surfaces, forming a blanket second refractory metal layer over the device, forming a blanket .alpha.-Si layer over the second refractory metal layer, forming a mask over the device to pattern an interconnect between the separate regions, then etching away the unwanted portions of the refractory metal layers and the .alpha.-Si layer, performing a rapid thermal annealing process on the device forming a low resistance refractory metal silicide between the .alpha.-Si layer and the second refractory metal layer, and then etching away the unwanted portions of the refractory metal layers that are not covered by the refractory metal silicide.

Growing community of inventors

Singapore, Singapore

Yeow Meng Teo