Mediatek Corporation

Yeow-Chyi Chen

Hong-Ching Chen

Li-Chun Tu

Tzu-Chieh Lin

Chi-Wei Peng

A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array.

Flash memory devices and methods for controlling a flash memory device

A buffer control system for generating a buffered signal having reduced buffer delay time between playback of tracks includes a controller module for providing an end target and for selection of a servo data signal corresponding to a desired track; a compare circuit coupled to the servo data signal for comparing a timestamp of the servo data signal to the end target, and asserting an end match signal when the timestamp of the servo data signal matches the end target; and a data buffering unit for storing the servo data signal as stored data to fill a capacity of an internal memory, and streaming out the buffered signal from the stored data in the internal memory when the capacity has reached a predetermined level; wherein the controller module is for updating selection of the servo data signal according to a next desired track upon assertion of the end match signal.

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Taipei, Taiwan

Yeow-Chyi Chen