Taiwan Semiconductor Manufacturing Comp. Ltd.

Yeou-Lang Hsieh

Chin-Min Lin

Jiann-Jong Wang

Ching-Kun Huang

Yi-Jing Chu

Ching-Kwun Huang

Jeng-Dong Sheu

A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency includes first depositing a first dielectric having an optically transparent property on and around a metal pattern. Optical sensors are formed in or on the substrate in areas between metal features. The metal pattern protects a sensor situated therebetween and thereunder from electromagnetic radiation. After the first dielectric layer is polished using CMP, a slanted or inclined surface is produced but this non-uniformity is eliminated using further planarization processes that produce a uniform total dielectric thickness for the proper functioning of the sensor.

Methods for planarization of dielectric layer around metal patterns for optical efficiency enhancement

A memory device includes a first memory cell area having a first latch area where one or more electronic components are constructed for storing a value, and a first peripheral area surrounding the first latch area; and a second memory cell area being disposed adjacent to a first side of the first memory cell area, and having a second latch area where one or more electronic components are constructed for storing a value, and a second peripheral area surrounding the second latch area. One edge of the first memory cell area shifts away from its corresponding edge of the second memory cell area. Thus, the area or yield rate of the memory device can be adjusted.

Stagger memory cell array

RF devices formed in integrated circuit devices include a top metal level overlying a substrate. The top metal level comprises pads and portions of planned RF devices and an RF metal level overlying the top metal level completes the RF devices which may be an interconnected RF network that may include capacitors, inductors or both. Openings are formed in a passivation layer overlying the RF metal level to provide direct access to the RF devices. The interconnected RF network may include fuses enabling the network to be selectively altered by cutting relatively thin interconnect lines using a laser directed through the openings. The RF devices or portions of the RF network may be directly coupled to external devices and utilized in SOC (System On a Chip) and SIT (System In Package) technologies.

Capacitor and inductor scheme with e-fuse application

A new method to form RF devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A top metal level is defined overlying the substrate. The top metal level comprises pads and portions of planned RF devices. A first passivation layer is formed overlying the top metal level. The first passivation layer is patterned to selectively expose the pads and the parts of planned RF devices. A dielectric layer is formed overlying the top metal level and the first passivation layer. The dielectric layer is patterned to selectively expose the top metal level. An RF metal level is defined overlying the dielectric layer and the top metal level to thereby complete the RF devices. A second passivation layer is formed overlying the RF metal level, the dielectric layer, and the top metal level. The second passivation layer is patterned to expose the pads. The method is disclosed for damascene and non-damascene metal.

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Taipei, Taiwan

Yeou-Lang Hsieh