Lg Display Co., Ltd.

Yeonwoo Shin

Yewon Hong

TaeWoong Moon

Yeonkyung Kim

JunHyeon Bae

JungHyun Lee

One or more embodiments of the present disclosure relate to a display device and a gate driving circuit. There is further provided with a synchronization transistor controlled according to a voltage of a Q node of a m-th scan driver (e.g., a second scan driver) and controlling an electrical connection between an output terminal of the n-th light emitting driver and a clock input terminal of the m-th scan driver, so that the rising characteristic and/or the falling characteristic of the light emission signal which is a type of the gate signal can be improved, thereby improving a threshold voltage compensation performance of the driving transistor and the image quality.

Display device and gate driving circuit having a synchronization transistor

A display apparatus comprises a display panel on which a plurality of pixels are displayed, a plurality of signal lines to which a signal required to drive the display panel is supplied, and an electrostatic discharge circuit connected between each of the plurality of signal lines and the electrostatic discharge line. The electrostatic discharge circuit includes first and second current paths between the signal line and the electrostatic discharge line, a first electrostatic discharge circuit connected to the first current path, including a plurality of first thin film transistors having a first gate electrode connected to the second current path and a second gate electrode connected to the first current path, and a second electrostatic discharge circuit connected to the second current path, including at least one second thin film transistor having a first gate electrode connected to the first current path and a second gate electrode connected to the first current path.

Display apparatus

A display apparatus includes first to third demultiplexer circuits respectively providing a data signal, supplied from a data driver, to three data lines. Each of the first to third demultiplexer circuits includes a switching unit providing the data signal to a corresponding data line of the three data lines on the basis of a voltage of a corresponding control line of first to third control lines, a voltage controller controlling the voltage of the corresponding control line in response to a corresponding time division control signal of first to third time division control signals and a corresponding auxiliary signal of first to third auxiliary signals which partially overlap the first to third time division control signals respectively, and a voltage discharger discharging the voltage of the corresponding control line.

A display device having a gate driver, which may reduce a leakage current of a TFT and power consumption, is disclosed. Each stage of the gate driver comprises an output portion including a pull-up transistor outputting a corresponding clock of a plurality of clocks as a gate signal in response to control of a Q node, and a pull-down transistor outputting a first gate-off voltage as an off-voltage of a gate signal in response to control of a QB node; a controller charging and discharging the Q node and charging and discharging the QB node to be in an opposite state of the Q node; and a back bias circuit having a back bias node capacitance-coupled with the Q node and generating a second gate-off voltage lower than the first gate-off voltage to apply the second gate-off voltage to the back bias node for an off-period of the Q node, wherein the back bias circuit may apply the back gate bias voltage to light shielding layers of some transistors, which are turned off for the off-period of the Q node, among transistors constituting the output portion and the controller, through the back bias node, thereby reducing or minimizing a leakage current of the corresponding transistors.

Display device having gate driver

A display device having a gate driver, which may reduce a leakage current of a TFT and power consumption, is disclosed. Each stage of the gate driver comprises an output portion including a pull-up transistor outputting a corresponding clock of a plurality of clocks as a gate signal in response to control of a Q node, and a pull-down transistor outputting a gate-off voltage as an off-voltage of a gate signal in response to control of a QB node; a controller charging and discharging the Q node and charging and discharging the QB node to be in an opposite state of the Q node; and a back bias circuit having a back bias node capacitance-coupled with the Q node and generating a back gate bias voltage to apply the back gate bias voltage to the back bias node for an off-period of the Q node, wherein the back bias circuit may apply the back gate bias voltage to light shielding layers of some transistors, which are turned off for the off-period of the Q node, among transistors constituting the output portion and the controller, through the back bias node, thereby reducing or minimizing a leakage current of the corresponding transistors.

Growing community of inventors

Paju-si, South Korea

Yeonwoo Shin