Samsung Electronics Co., Ltd.

Yeonggeol Song

Kijun Lee

Sunghye Cho

Myungkyu Lee

Sungrae Kim

Eunae Lee

Chanki Kim

Junjin Kong

Yesin Ryu

Jinhoon Jang

Isak Hwang

Kyomin Sohn

Jaeyoun Youn

Sanguhn Cha

Sukhan Lee

Sung-Rae Kim

Sunggi Ahn

Byeonggyu Park

Seokha Hwang

A memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer managing circuit, which is configured to detect a row hammer address based on a pre row hammer address, and each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to a plurality of the rows of memory cells. A refresh control circuit is provided and is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.

Memory devices and methods thereof for managing row hammer events therein

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

Semiconductor memory device and method of operating the same

A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.

Memory device performing refresh operation and method of operating the same

A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

Semiconductor memory devices

A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.

Semiconductor memory devices and memory systems

A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.

Semiconductor memory devices with ECC engine defect determination based on test syndrome, test parity, expected decoding status and received decoding status

A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.

Semiconductor memory devices and methods of operating semiconductor memory devices

An error correction device according to the technical idea of the present disclosure includes a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generation circuit configured to generate partial coefficient information on a part of a coefficient of an error location polynomial by using the data while the plurality of syndromes are generated, an error location determination circuit configured to determine the coefficient of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data according to the location of the error.

Error correction device and method for generating syndromes and partial coefficient information in a parallel

A method for reading data from a memory includes; reading a codeword from the memory cells, correcting the errors when a number of errors in the codeword is less than a maximum number of correctable errors, correcting the errors when the number of errors in the codeword is equal to the maximum number of correctable errors and the errors correspond to a same sub-word line, and outputting signal indicating that the errors are an uncorrectable error when the number of errors of the codeword is equal to the maximum number of correctable errors and the errors correspond to different sub-word lines.

Memory device and method reading data

A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.

Memory controllers and memory systems including the same

A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder to perform an ECC decoding on a codeword including a main data and a parity data, read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on a command and address from an external memory controller. The ECC decoder has t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during (t&#x2212;2) cycles to generate an error locator polynomial based on the syndrome, searches error positions in the codeword based on the error locator polynomial and corrects the errors in the codeword based on the searched error positions.

An error correction circuit includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates, based on a main data, a parity data using an ECC represented by a generation matrix and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page as a read codeword based on an externally provided address to generate different syndromes based on the read codeword and a parity check matrix which is based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells in the target page.

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Seoul, South Korea

Yeonggeol Song