Via Technologies, Inc.

Via Alliance Semiconductor Co., Ltd.

Shanghai Zhaoxin Semiconductor Co., Ltd.

Yeong-Sheng Lee

George Shing

Kuangda Chu

Kuen-Chir Wang

Scott Kuenchir Wang

Winsheng Cheng

An output driving system includes an output driver, a first ESD (Electrostatic Discharge) protection circuit, a second ESD protection circuit, a first differential amplifier, a second differential amplifier, a first capacitor, and a second capacitor. The output driver has a first output node for outputting a first output voltage, and a second output node for outputting a second output voltage. The first differential amplifier generates a first amplified voltage according to the first output voltage and the second output voltage. The first capacitor has a first terminal for receiving the first amplified voltage, and a second terminal coupled to the first output node. The second differential amplifier generates a second amplified voltage according to the first output voltage and the second output voltage. The second capacitor has a first terminal for receiving the second amplified voltage, and a second terminal coupled to the second output node.

Output driving system with capacitance compensation

A reference voltage generation circuit for generating an output voltage is provided. The reference voltage generation circuit includes a bandgap reference circuit and a voltage adjustment circuit. The bandgap reference circuit generates the output voltage at an output node and a reference voltage. The voltage adjustment circuit is coupled to the bandgap reference circuit. The voltage adjustment circuit receives the output voltage and the reference voltage, compares the output voltage with the reference voltage to generate a comparison result, and adjusts the output voltage according to the comparison result.

Reference voltage generation circuit insensitive to element mismatch

A skew compensation circuit includes a common mode generator, a common mode comparator, a common mode detector, and a skew adjustment circuit. The common mode generator generates a common mode voltage according to a first input voltage and a second input voltage. The common mode comparator generates a first comparison voltage and a second comparison voltage according to the common mode voltage. The common mode detector generates a first control voltage, a second control voltage, a third control voltage, and a fourth control voltage according to the first comparison voltage, the second comparison voltage, a first data voltage, and a second data voltage. The skew adjustment circuit generates a first output voltage and a second output voltage according to the first data voltage, the second data voltage, the first control voltage, the second control voltage, the third control voltage, and the fourth control voltage.

Skew compensation circuit

A pre-driver for driving an LVDS (Low Voltage Differential Signaling) driving circuit is provided. The pre-driver includes a first inverter, a high-pass filter, and a second inverter. The first inverter has an input terminal coupled to an input node of the pre-driver, and an output terminal coupled to a first node. The high-pass filter is coupled between the first node and a second node. The second inverter has an input terminal coupled to the second node, and an output terminal coupled to an output node of the pre-driver. The high-pass filter is configured to improve a high-frequency response of the pre-driver.

Pre-driver for driving low voltage differential signaling (LVDS) driving circuit

An interpolator includes a first delay circuit, a second delay circuit, and a tunable delay circuit. The first delay circuit delays a first input signal for a fixed delay time, so as generate a first output signal. The second delay circuit delays a second input signal for the fixed delay time, so as to generate a second output signal. The tunable delay circuit delays the first input signal for a tunable delay time, so as to generate an output interpolation signal. The tunable delay time is determined according to the first output signal, the second output signal, and the output interpolation signal.

Interpolator

A low-voltage-drop rectifier circuit includes a first MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a second MOSFET, a comparator, and a level adjustment circuit. The first MOSFET has a gate terminal for receiving a control voltage, a source terminal connected to a connection node, a drain terminal connected to an input node, and a body terminal connected to the connection node. The second MOSFET has a gate terminal for receiving the control voltage, a source terminal connected to an output node, a drain terminal connected to the connection node, and a body terminal connected to the output node. The comparator generates a first comparison voltage and a second comparison voltage according to an input voltage at the input node and an output voltage at the output node. The level adjustment circuit generates and fine-tunes the control voltage according to the first comparison voltage and the second comparison voltage.

Low-voltage-drop rectifier circuit

A single-ended-to-differential converter for driving an LVDS (Low Voltage Differential Signaling) driving circuit includes a first converting circuit, a second converting circuit, and a controller. The first converting circuit converts an input signal into a first output signal. The first converting circuit has a tunable delay time. The second converting circuit converts the input signal into a second output signal. The second converting circuit has a fixed delay time. The controller generates a first control signal and a second control signal according to the first output signal and the second output signal, so as to adjust the tunable delay time of the first converting circuit.

Single ended-to-differential converter

A CDR (Clock and Data Recovery) circuit includes a current source, an operational amplifier, an NOR gate, and a capacitor. The current source supplies a current to a first node. The operational amplifier has a positive input terminal for receiving a reference voltage, a negative input terminal coupled to the first node, and an output terminal coupled to a second node. The NOR gate has a first input terminal coupled to the second node, a second input terminal coupled to an input node of the CDR circuit, and an output terminal coupled to an output node of the CDR circuit. The input node is arranged for receiving an input signal, and the output node is arranged for outputting an output signal. The capacitor is coupled between the first node and the output node.

Clock and data recovery circuit

A pre-driver includes a first inverter, a second inverter, a third inverter, a first amplifier, a second amplifier, a third amplifier, a first capacitor, a second capacitor, and a third capacitor. The first inverter has an input terminal coupled to an output node, and an output terminal coupled to a first node. The second inverter has an input terminal coupled to the first node, and an output terminal coupled to a second node. The third inverter has an input terminal coupled to the second node, and an output terminal coupled to the output node. The output node is further coupled through the first amplifier and the first capacitor to the first node. The first node is further coupled through the second amplifier and the second capacitor to the second node. The second node is further coupled through the third amplifier and the third capacitor to the output node.

Ring oscillator

A pre-driver includes a first inverter, a second inverter, an amplifier, a first capacitor, and a second capacitor. The first inverter has an input terminal for receiving an input signal at an input node, and an output terminal coupled to an inner node. The second inverter has an input terminal coupled to the inner node, and an output terminal for outputting an output signal at an output node. The amplifier is configured to amplify the input signal by a gain factor so as to generate an amplified signal and an inverted amplified signal. The first capacitor has a first terminal coupled to the output node, and a second terminal for receiving the amplified signal. The second capacitor has a first terminal coupled to the inner node, and a second terminal for receiving the inverted amplified signal.

Pre-driver and replica circuit and driver system with the same

A detection circuit for detecting an external device with a specific resistance is provided. The detection circuit includes a first resistor, a second resistor, a first converter, a second converter, a device converter, a first current comparator, and a second current comparator. The first resistor has a first resistance. The second resistor has a second resistance. The first converter is configured to convert the first resistance into a first current. The second converter is configured to convert the second resistance into a second current. The device converter is configured to convert the specific resistance into a specific current. The first current comparator is configured to compare the specific current with the first current, and generate a first output signal. The second current comparator is configured to compare the specific current with the second current, and generate a second output signal.

Detection circuit

A phase detector includes a clock delay circuit, a data delay circuit, a control circuit, a D flip-flop, and a logic circuit. The clock delay circuit delays a clock signal so as to generate a delay clock signal. The data delay circuit delays a data signal so as to generate a delay data signal. The control circuit adjusts the delay time of the clock delay circuit and the delay time of the data delay circuit according to the clock signal and the delay clock signal. The D flip-flop generates a register signal according to the data signal and the clock signal. The logic circuit generates an up control signal and a down control signal according to the data signal, the delay data signal, and the register signal so as to control a charge pump of a CDR (Clock Data Recovery) circuit.

Phase detector for clock data recovery circuit

A power supply decoupling circuit includes an operational amplifier, a capacitor, a source resistor, and a stabilization circuit. The operational amplifier has a positive input terminal coupled to a first reference voltage, a negative input terminal coupled to a common supply node, and an output terminal. The capacitor is coupled between the common supply node and the output terminal of the operational amplifier. The source resistor is coupled between a supply voltage and the common supply node. The stabilization circuit is coupled between the common supply node and a ground voltage. The stabilization circuit stabilizes a voltage level of the common supply node when the voltage level of the common supply node is below a second reference voltage. The common supply node is configured to drive external circuits with the supply voltage as power supply of the external circuits.

Power supply decoupling circuit with decoupling capacitor

A charge pump includes a switching circuit, a constant current source, a constant current sink, an adaptive current source, and an adaptive current sink. The switching circuit generates an output voltage at an output node according to an up control signal and a down control signal. The constant current source supplies a first current to the switching circuit. The constant current sink draws a second current from the switching circuit. The adaptive current source supplies a third current to the switching circuit. The adaptive current sink draws a fourth current from the switching circuit. The third current and the fourth current are adjustable according to the up control signal and the down control signal.

Charge pump for use in phase-locked loop

An LVDS (Low Voltage Differential Signaling) driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, and a bias driver. The first transistor is coupled between a supply voltage and a first node. The second transistor is coupled between the supply voltage and a second node. The third transistor is coupled between the first node and a ground voltage. The fourth transistor is coupled between the second node and the ground voltage. The first resistor is coupled between the first node and a third node. The second resistor is coupled between the second node and the third node. The bias driver generates bias signals for controlling the first, second, third, and fourth transistors according to a data signal.

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Fremont, CA, United States of America

Yeong-Sheng Lee