Tsinghua University

Yeong-Luh Ueng

Chia-Hsiang Yang

Chin-Liang Wang

Yu-Lun Wang

Mao Ruei Li

Tsung-Chieh Yang

Mao-Ruei Li

Hsueh-Chih Chou

Kuan-Chieh Wang

Chung-Hsuan Wang

Hsin-Yu Lee

Chung-Jay Yang

Yu-Sheng Pao

Kuo-Hsuan Liao

Chen-Yap Leong

Yi-Han Pan

Chun-Jung Chen

Wei-Min Lai

Wei-Cheng Sun

Wei-Hsuan Wu

Yu-Heng Lin

Jyun-Kai Hu

The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.

Method and polar code decoder for determining to-be-flipped bit position

A successive cancellation list-based decoder and a decoding method thereof are provided. In the method, an error check is performed on a set of data bits. A data unit includes the set of the data bits and at least one first check bit. Part of the set of data bits are considered as at least one second check bit. At each of the second check bits, its previous error-check result are verified, where the verified result is related to a comparison between each of the previous first check bits and a value obtained through a function calculation on corresponding data bits. The verified result at each of the second check bits determines whether to continue decoding of the set of data bits or to early terminate the decoding process. The method is able to increase the probability for early termination of the decoding process and to improve the decoding efficiency.

Successive cancellation list-based decoder and decoding method thereof

The disclosure provides a non-orthogonal multiple access data transmission method and a transmission device using the same. The method includes: performing channel encoding for a plurality of data and a plurality of identifiers respectively corresponding to the plurality of data by using Raptor code so as to generate a Raptor codeword, wherein the plurality of identifiers respectively correspond to a plurality of receiving terminals; and modulating the Raptor codeword to generate a plurality of modulation symbols and broadcasting the plurality of modulation symbols.

Non-orthogonal multiple access data transmission method and transmission device

An iterative decoding device applied for a SISO (soft input soft output) system is disclosed, which comprises an operational control unit, a first decoder, and a second decoder. The operational control unit is operative to receive an encoded signal and divide the encoded signal into at least one frame. The first decoder is operative to receive each of the at least one frame and derive a renewed intrinsic information by a first iteration operation. The second decoder is operative to derive soft-information by a second iteration operation based on the renewed intrinsic information, and then transmit the soft-information back to the first decoder for the iteration operation of the next renewed intrinsic information. The operational control unit makes the at least one frame to be calculated respectively by the first decoder and the second decoder, thereby improving the efficiency and error ratio of a receiver.

SISO (soft input soft output) system for use in a wireless communication system and an operational method thereof

An extreme index finder and a digital value finding method are provided. The extreme index finder includes a plurality of digital-to-time converters (DTCs) and a first arbiter apparatus. The DTCs respectively receive a plurality of input signals and perform a digital-to-time converting operation on each of the input signals to respectively generate a plurality of time-domain signals. The first arbiter apparatus finds a position of a extreme value in the time-domain signals according to transition speeds of the time-domain signals and compares transition speed of the extreme value with each of the time-domain signals to find an extreme input signal corresponding to the extreme value in the input signals.

Extreme index finder and finding method thereof

An unequal bit-reliability information storage method for communication and storage systems at least includes one storage unit having a first memory and a second memory; the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory. Based on the significance of each bit of the information with the use of the first or second memories of different reliability for storage, the complexity of the storage unit, the production cost and the power consumption can be reduced while maintaining the performance.

Unequal bit reliability information storage method for communication and storage systems

A layered decoding architecture with a reduced number of hardware buffers for low-density parity-check (LDPC) decoding by storing a variable-to-check message. When a check node begins a new operation, a variable-to-check message (Q) is added to a check-to-variable message (R) obtained in previous check-node operation to obtain an updated APP value. Then, the R value for the check node in the layer being processed is deducted from the APP value to obtain a variable-to-check message (Q). This variable-to-check message is stored in the memory and inserted into the check node equation to obtain a check-to-variable message. Finally the check-to-variable message obtained in this operation is stored to the check-to-variable message shift register to complete the updating operation for the check node and the variable node for the layer being processed. Improved hardware utilization and fewer buffers, thus achieving a smaller hardware area while retaining the converge speed, is obtained.

Layered decoding architecture with reduced number of hardware buffers for LDPC codes

A system providing early termination for channel decoding by re-encoding including a decoding unit, an encoding unit connected to the decoding unit, and a checking unit connected to the decoding unit and to the encoding unit. Via the system, decoded message words produced from the decoding unit are sent back to the encoding unit for re-encoding. Re-encoded words are compared to the decoded codewords by the checking unit and, if they are completely the same, the decoding action of the decoding unit is terminated. The system reduces power consumption and offers a simplified structure, improved decoding throughput, and reduced hardware complexity.

Method of early termination of channel decoding by re-encoding

The present invention provides a low-complexity and multi-mode Low-density Parity-check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified hardware is implemented so that the hardware resources can be reused in different modes. In addition, memory access is achieved via routing networks with fixed interconnections and memory address generators, the complexity of the hardware implementation is reduced accordingly. Further, the present invention provides an early termination function with which the iterative operations can be terminated early when a threshold is reached so that the power consumption can be thus reduced. The hardware resources for early termination shares a part of hardware resources with an encoder according to the present invention so that the complexity of the hardware implementation can also be reduced.

Low density parity check codec

A non-binary quasi-cyclic (QC) low-density parity-check (LDPC) code decoding device comprises a first barrel-shifter, a routing network and a second barrel-shifter. The first barrel-shifter uses a constraint h'v&#x2032;+h&#x2033;v&#x2033;=hv to shift q&#x2212;1 elements of an input by jpositions to produce first temporary elements. The routing network connects to the first barrel-shifter, permutes the first temporary elements to produce second temporary elements if v&#x2032; of the constraint is not zero and designates the first temporary elements as the second temporary elements if v&#x2032; of the constraint is zero. The second barrel-shifter connects to the routing network and uses the constraint h&#x2032;v&#x2032;+h&#x2033;v&#x2033;=hv to shift q&#x2212;1 elements of the second temporary elements by ipositions. A non-binary QC-LDPC decoding method is also disclosed.

Non-binary QC-LDPC code decoding device and associated method

Configurable permutators in an LDPC decoder are provided. A partially-parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multi-mode function. To overcome the difficulty in efficient implementation of a high-throughput decoder, the variable nodes are partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and, hence, increase the maximum operating frequency. In addition, shuffled message-passing decoding can be adopted in decoders according to the invention to increase the convergence speed, which reduces the number of iterations required to achieve a given bit-error-rate performance.

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Hsinchu, Taiwan

Yeong-Luh Ueng