Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Industry-university Cooperation Foundation Hanyang University

Yeong-Keun Kwon

Ji-Sun Kim

Chong-Chul Chai

Soo-wan Yoon

Jae-Keun Lim

Jong-Hee Kim

Yoon-Jang Kim

Dong-Gyu Kim

Oh-Kyong Kwon

Young Wan Seo

Young-Soo Yoon

Ji-Hyun Kim

Jong-Woong Chang

Jae Keun Lim

Kee-Bum Park

Chongchul Chai

Shin-Il Choi

Ki-Won Kim

Woo-Geun Lee

Kyung-Ho Park

Bon-Yong Koo

Jong Hee Kim

Jeong-Il Kim

Bae-Heuk Yim

Sung-Man Kim

Chong Chul Chai

Kwang-chul Jung

Jaehoon Lee

Bonghyun You

Young-Wook Lee

Seong-Young Lee

Bong Hyun You

Jin-Won Lee

Kap-Soo Yoon

Kuk-Hwan Ahn

Hye-Young Ryu

Sung Man Kim

Duk-Sung Kim

Jean-Ho Song

Jai-Hyun Koh

Eun Jeong Cho

Mi-Sun Lee

Sang-Jin Jeon

Hyun-Jung Lee

Min-Chul Song

Min-cheol Lee

Heendol Kim

Soon-Il Ahn

Soo Jung Chae

Mi-Seon Seo

Jong Hyuck Kim

Eu Gene Lee

Yun-Hee Kwak

Ju-Hee Lee

Se-Young Song

Chong-Chui Chai

Jong-Woon Chang

ChongChel Chai

Eung Cho

A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.

Display substrate comprising a plurality of conductive patterns

A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Display panel

A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Stage circuit including a controller, drivers, and output units and scan driver using the same

Scan driver including stage circuit for reducing leakage current

A liquid crystal display according to an embodiment of the present invention includes: a first substrate; a plurality of color filters formed on the first substrate and arranged in a matrix with an island shape; a plurality of pixel electrodes formed on the color filters; and a capacitor disposed between neighboring color filters in a column direction among the color filters, wherein two terminals forming the capacitor are disposed at a portion outside a position overlapping the color filters.

Liquid crystal display

A mother substrate includes a display substrate cell defined by a scribe line, the display substrate cell including a plurality of gate lines, a gate circuit part driving the gate lines, and a gate pad part connected to the gate circuit part, a gate test pad part in a peripheral area surrounding the display substrate cell, the gate test pad part being configured to receive a gate test signal, a gate test line part connecting the gate test pad part and the gate pad part, and a switching part connected to the gate test line part and configured to control turning on and turning off of the gate test line part.

Mother substrate with switch disconnecting test part, array test method thereof and display substrate

A gate driver, including multiple stages of gate driving circuits, wherein each stage of the gate driving circuits includes an input part configured to generate a Q node signal in response to a carry signal of one of previous stages and a clock signal, the Q node signal being applied to Q node, an output part configured to output a gate output signal to a gate output terminal in response to the Q node signal, and a charge sharing part connected to the gate output terminal of a present stage and a gate output terminal of one of next stages, the charge sharing part configured to operate charge-sharing between the gate output signal of the present stage and a gate output signal of one of the next stages in response to a select signal.

Gate driver and display apparatus having the same

A liquid crystal display panel with enhanced image quality is disclosed. The liquid crystal display panel has a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to gate line and data line, a plurality of pixel electrodes, and floating electrode(s). The floating electrode extends along the data line to prevent light leakage and vertical crosstalk. Throughout the whole liquid crystal display panel, the floating electrode is electrically interconnected to lessen vertical crosstalk.

Liquid crystal display panel having a light blocking electrode

A display device includes pixels, gate lines, and data lines on a substrate. The pixels include sub-pixels, and each sub-pixel includes a respective one of a plurality of first electrodes connected to one of the gate lines and one of the data lines. The first electrode of the sub-pixel at an n-th row and the first electrode of the sub-pixel at an (n+2)-th row in a same column are connected to different ones of the data lines. The sub-pixels in the n-th and (n+2)-th rows in the same column emit the same color of light.

Display device

A display apparatus includes gate lines, data lines insulated from the gate lines while crossing the gate lines, and pixels each including sub-pixels in two successive rows by three successive columns. Among the sub-pixels in the two rows by the three columns, the sub-pixels in one of the three columns are respectively connected to a pair of different gate lines among three gate lines, and the sub-pixels in a different one of the three columns are connected to a remaining gate line among the three gate lines. The sub-pixels in the one and the different one of the three columns includes the same color filter and are applied with a gate signal transmitted in the same direction along pixel rows.

Display apparatus

A gate driver circuit includes an N-th stage ('N' is a natural number) The N-th stage ('N' is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (&#x2018;n&#x2019; is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Gate driver in which each stage thereof drives multiple gate lines and display apparatus having the same

A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Stage circuit and scan driver using the same

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Yongin-si, South Korea

Yeong-Keun Kwon