Samsung Electronics Co., Ltd.

Yeong Geol Song

Jun Jin Kong

Hong Rak Son

Dong Min Shin

Beom Kyu Shin

Heon Hwa Cheong

Se Jin Lim

Ki Jun Lee

Jin-Hoon Jang

Sung-Rae Kim

Myung Kyu Lee

A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

Memory device and memory system including the same

A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Method of operating decoder for reducing computational complexity and method of operating data storage device including the decoder

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Seoul, South Korea

Yeong Geol Song