Skhynix Inc.

Yeong Dong Gim

Jee Yul Kim

Dong Hyun Cho

Jung Ae Kim

Jang Hwan Jun

The present disclosure relates to an electronic device. A memory system according to the present disclosure includes a memory device including memory blocks each including a plurality of pages, a buffer memory configured to store information including a fail count of a cache read operation corresponding to each of the memory blocks, and a memory controller configured to control the memory device to perform a normal read operation or the cache read operation on a target memory block based on the fail count corresponding to the target memory block among the memory blocks.

Memory controller controlling cache read operation, memory system including the memory controller, and method of operating the same

A storage device may execute first error correction decoding on a plurality of memory cells when a read operation on the plurality of memory cells fails, and determine, when the first error correction decoding fails, whether to execute second error correction decoding on the plurality of memory cells based on at least one of a value of an early termination flag and whether an early termination condition is satisfied.

Storage device determining quickly whether error correction decoding has failed and method of operating the storage device

A data storage device may include a nonvolatile memory device, and a controller configured to increase an assert count, when a malfunction occurs while an operation for a command received from a host device is executed, the assert count representing the number of times the malfunction has occurred, and execute a flash translation layer (FTL) resetting operation in a read-dedicated mode in response to an initialization request from the host device when the assert count is greater than or equal to a reference value.

Data storage device and operating method thereof

An operating method of a memory system that includes a memory device including a plurality of blocks and a controller including a memory in which a first open block list and a second open block list are stored, the method comprising receiving a write request and a logical address from a host; converting the logical address into a first virtual address; converting the first virtual address into a physical address; performing a first error checking operation of checking a mapping relationship between the first virtual address and the physical address based on the first open block list; performing a second error checking operation of checking whether the physical address is included in the second open block list; and performing a write operation on an open block corresponding to the physical address when it is determined that the physical address is not allocated more than once.

Memory system and method of operating method thereof

Provided herein may be a memory controller and an operating method thereof. The memory controller may include: a read fail control circuit configured to perform, when the read operation fails, an assist read operation of determining optimal read voltages to be used to read the selected memory cells, and determine whether a threshold voltage distribution of the selected memory cells is an abnormal distribution based on read-related information obtained by the read operation and the assist read operation; and an error correction code (ECC) engine configured to perform an ECC decoding operation on hard decision data obtained by reading the selected memory cells using the optimal read voltages based on whether the threshold voltage distribution of the selected memory cells is the abnormal distribution.

Memory controller and method of operating the same

An operation method of a memory system includes performing a first read operation on a word line corresponding to a read command, using a read voltage set including a first read voltage; performing a second read operation on the word line using a second read voltage greater than the first read voltage, depending on whether error correction on data read through the first read operation fails; and determining a memory block that includes a memory cell to which the word line is coupled as a closed memory block, depending on whether the word line is determined to be an erased word line as the result of the second read operation.

Memory system for detecting erased page including memory cells with distorted threshold voltages, and operation method thereof

A memory system includes a nonvolatile memory device including a CAM (content addressable memory) region; and a controller including a random access memory which stores an initial setting parameter of the nonvolatile memory device and a control unit which controls an initializing operation for a setting parameter of the nonvolatile memory device stored in the CAM region, wherein the control unit includes a parameter determination circuit which determines whether the initializing operation has succeeded or not, by comparing a verify parameter received from the nonvolatile memory device and the initial setting parameter.

Memory system and operating method thereof

A data storage device includes a nonvolatile memory device and a controller which controls the nonvolatile memory device. When the data storage device is powered on after a sudden power off (SPO), the controller detects an erased page by scanning, without decoding, a first system data block of a nonvolatile memory device, performs simple decoding for first system data of first system pages before the erased page, and, if the simple decoding is a fail, recovers the first system data for which the simple decoding failed, by reading out second system data from corresponding second system pages of a second system data block as a duplicate block of the first system data block.

A data storage device includes a nonvolatile memory device; and a controller configured to include a plurality of cores, wherein, when an error occurs in at least one core among the cores, a first core which is coupled with the nonvolatile memory device transmits state records of one or more core among the cores at an error occurrence time, to the nonvolatile memory device.

Collecting state records of cores in a data storage device

A data storage device includes a nonvolatile memory device including a plurality of memory cells; and a controller suitable for determining whether the memory cells are erased or not, wherein, when it is determined, based on first data read as a read voltage set including a first read voltage is applied to the memory cells, that the memory cells are not erased, the controller determines whether the memory cells are erased or not based on second data read as the read voltage set in which the first read voltage is replaced with a second read voltage is applied to the memory cells, and wherein the first and second read voltages are read voltages of lowest levels among read voltages included in the read voltage set.

Growing community of inventors

Gyeonggi-do, South Korea

Yeong Dong Gim