Skhynix Inc.

Yeon Uk Kim

Jeong Tae Hwang

Hoon Moo Choi

Sang Don Lee

Seok Joon Kang

Jae Boum Park

An internal voltage generation circuit includes a comparison circuit, a driving signal generation circuit and a driving circuit. The comparison circuit generates a comparison signal from an internal voltage in response to a reference voltage. The driving signal generation circuit generates a pull-up driving signal and a pull-down driving signal having different duty ratios in response to the comparison signal. The driving circuit drives the internal voltage in response to the pull-up driving signal and the pull-down driving signal.

Internal voltage generation circuit

A semiconductor integrated circuit device having a bulk bias control function is provided. The semiconductor integrated circuit device may be configured to output the first external voltage as a bulk voltage of a transistor in a power-up period, and to output a second external voltage having a higher level than the first external voltage as the bulk voltage of the transistor in a power-down mode.

Semiconductor integrated circuit device having bulk bias control function and method of driving the same

A power-supply voltage sensing device is disclosed, which relates to a technology for detecting a level of an external power-supply voltage during a test mode. The power-supply voltage sensing device includes a reference voltage trimming unit configured to trim a reference voltage in response to a code signal, a power-supply voltage detection unit configured to select one of a power-supply voltage and an external power-supply voltage in response to a test signal, compare the external power-supply voltage with the reference voltage, and output a detection signal according to the result of comparison, and a reference voltage control unit configured to output the code signal in response to the detection signal.

Power-supply voltage sensing device

An internal voltage generation device includes a voltage generation block configured to compare a reference voltage and a divided voltage, and generate an output voltage; and an internal voltage driving block including a pull-up driving unit which selectively pull-up drives an internal voltage according to the output voltage, and configured to output the output voltage to the pull-up driving unit through different paths according to a test signal.

Internal voltage generation device

A system includes a power supply, a memory controller and a memory device. The memory controller is configured to receive power from the power supply, generate a memory power supply voltage for use by the memory device based on the power received from the power supply and provide the memory power supply voltage to the memory device.

System including memory controller for managing power of memory

The semiconductor device includes a power control signal generator, a fuse controller and a fuse array portion. The power control signal generator generates a power control signal enabled during a predetermined period from a termination moment of a power-up period and enabled in response to a test mode signal. The fuse controller generates a boot-up signal enabled if a reboot-up signal is inputted during an enablement period of the power control signal. The fuse controller also generates a fuse reset signal enabled if a reset signal is inputted after a clock training operation. The fuse array portion generates a plurality of fuse data initialized if the fuse reset signal is enabled. The plurality of fuse data are programmed according to electrical open/short states of fuses in response to the power control signal.

Semiconductor devices

Semiconductor devices are provided. The semiconductor device may include a control signal generator and a fuse array portion. The control signal generator may generate a power control signal, disable the power control signal to a ground voltage signal level during a power-up period, and enable the power control signal to a power supply voltage signal level from a moment that the power-up period terminates until a moment that a mode register set operation terminates. The fuse array portion may execute a boot-up operation while the power control signal is enabled. The fuse array portion may generate fuse data according to an electrical open/short state of a fuse. The fuse may be selected by a level combination of address signals during the boot-up operation.

Semiconductor devices and semiconductor systems

A semiconductor memory apparatus according to the embodiment includes: an external connection terminal configured to supply an external voltage; a fuse unit configured to perform a fuse rupture operation; and an interruption circuit unit configured to respond to a test signal to determine whether the external connection terminal is connected to the fuse unit.

Growing community of inventors

Icheon-si, South Korea

Yeon Uk Kim