Skhynix Inc.

Yeon Seung Jung

Jong Hoon Kim

Jin Woo Park

Ki Jun Sung

Hyeong Seok Choi

Joo Wan Hong

A semiconductor package includes a package substrate, a plurality of memory stacks, at least one processor chip and one or more heat dissipation structures. The memory stacks are disposed on the package substrate. The memory stacks are spaced apart from each other by a predetermined distance. The processor chip is disposed on the memory stacks to be partially overlapped with each of the memory stacks. The heat dissipation structure is disposed on the upper surfaces of the memory stacks.

Semiconductor package having a three-dimensional stack structure

A semiconductor package and a method of manufacturing the semiconductor package may be provided. The semiconductor package may include a first semiconductor chip disposed on a first surface of an interconnection layer, a second and a third semiconductor chips disposed on a second surface of the interconnection layer. The semiconductor package may include a thermal transfer plate disposed between the second and third semiconductor chips, contacting the second surface of the interconnection layer, and overlapping with the first semiconductor chip. The thermal transfer plate may be configured to provide a heat radiation path.

Semiconductor packages relating to thermal transfer plate and methods of manufacturing the same

A semiconductor package and or method of fabricating a semiconductor package may be provided. The semiconductor package may include a package substrate. The semiconductor package may include a first semiconductor die coupled to the package substrate by first interconnectors. The semiconductor package may include a second semiconductor die coupled to the first semiconductor die by second interconnectors. The second semiconductor die may be coupled to the substrate.

Semiconductor packages including interconnectors and methods of fabricating the same

There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Growing community of inventors

Suwon-si, South Korea

Yeon Seung Jung