Samsung Electronics Co., Ltd.

Yeon-Kyu Choi

Ki-Seok Oh

Kyung-Soo Ha

Seok-Hun Hyun

Chang-Kyo Lee

Dae-Sik Moon

Jung-Hwan Choi

Gil-Hoon Cha

Seung-Jun Shin

Hye-Ran Kim

Young-Soo Sohn

Jin-Hoon Jang

A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Memory device adjusting duty cycle and memory system having the same

A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Method and memory system for optimizing on-die termination settings of multi-ranks in a multi-rank memory device

A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Memory device having a plurality of low power states

Various embodiments of the disclosure provide an apparatus for protecting information. According to various embodiments of the disclosure, an apparatus for monitoring a database includes a transceiver, and a processor operatively coupled to the transceiver. The processor may be configured to acquire a query used in access of the database from the database through the transceiver, replace a first code, included in the acquired query, for query checking to a predefined text, convert the text to a second code for query checking, and output information on validity of the acquired query on the basis of a comparison result of the first code and the second code.

Method for protecting information and device therefor

An electronic device according to an embodiment of the present invention comprises: a memory for storing a list including information related to the termination of one or more first applications of a plurality of applications included in the electronic device; and a processor, wherein the processor executes one or more second applications of the plurality of applications, checks contextual information associated with the electronic device, and, if the contextual information satisfies a specified condition, determines whether to terminate at least one executed application of the one or more executed second applications.

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Seoul, South Korea

Yeon-Kyu Choi