Arm Limited

Yeon Jun Park

Andy Wangkun Chen

Fakhruddin Ali Bohra

Lalit Gupta

Shri Sagar Dwivedi

Jitendra Dasani

Yicong Li

Sharryl Renee Dettmer

Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.

Transition coupling circuitry for memory applications

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San Jose, CA, United States of America

Yeon Jun Park