Samsung Electronics Co., Ltd.

Gct Semiconductor, Inc.

Yeon-jae Jung

Seung-wook Lee

Won-chan Kim

Chang-sik Yoo

Dae-yun Shim

Kee-wook Jung

Deok-hee Lee

A receiver includes a mixer configured to convert a radio frequency (RF) signal into a baseband, an impedance shaping unit configured to shape a magnitude of load impedance seen in an output terminal of the mixer in a frequency band of an interference signal converted into the baseband so as to reduce the magnitude of the load impedance, and a trans-impedance amplifier configured to amplify the signal converted into the baseband.

Receiver using impedance shaping

A duty cycle correction circuit includes a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.

Duty cycle correction circuits that reduce distortion caused by mismatched transistor pairs

A clock synchronization circuit is provided for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween. A second loop is adapted to delay the plurality of reference clock signals; select a signal from among the plurality of delayed reference clock signals; provide the selected signal to the clock buffer; detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal; generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages; so as to synchronize the internal clock signal with the external clock signal.

Clock synchronization circuit and semiconductor device having the same

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Kyungsangnam-do, South Korea

Yeon-jae Jung