Samsung Electronics Co., Ltd.

Yeon-Hong Jee

Byung-Suk Park

Ill-Hwan Jeoun

Tae-Hyo Ro

The semiconductor device comprises a silicon substrate, a first metal pattern layer which is deposited on the silicon substrate, an inter metal dielectric which is deposited on the silicon substrate including the first metal pattern layer and on which a connection hole is formed to partially expose the upper surface of the first metal pattern layer, a second metal pattern layer which is deposited on the inter metal dielectric and electrically interconnected to the first metal pattern layer by the connection hole, and a passivation layer which coats the silicon substrate including the second metal pattern layer and has an opening to partially expose the second metal pattern layer for electrically connecting the semiconductor device to external circuitry. The first metal pattern layer comprises a Ti/TiN layer, an Al layer, and a TiN layer, and the second metal pattern layer comprises a Ti layer and an Al layer. The passivation layer coats a portion of the second metal pattern layer, the portion being disposed on an inner portion of the connection hole. The present invention has some advantages in that it prevents the cutting of the Al layer on the concave corner of the second metal pattern layer and the exfoliating of the second metal pattern layer from the first metal pattern layer.

Method for manufacturing a semiconductor device

The semiconductor device includes a silicon substrate, a first metal pattern layer which is deposited on the silicon substrate, and an inter metal dielectric which is deposited on the silicon substrate including the first metal pattern layer and on which a connection hole is formed to partially expose the upper surface of the first metal pattern layer, the connection hole having concave corner portion formed on a side thereof. A second metal pattern layer is deposited on the inter metal dielectric and electriacally interconnects to the first metal pattern layer by the connection hole. A passivation layer coats the silicon substrate including the second metal pattern layer and the concave corner portion and has an opening to partially expose the second metal pattern layer for electrically connecting the semiconductor device to external circuitry. The passivation layer extends beyond the concave corner portion such that when the passivation layer is etched, the concave corner portion remains coated with the passivation layer to thereby protect the concave corner portion from damage due to subsequent processes. The first metal pattern layer comprises a Ti/TiN layer, an Al layer, and a TiN layer, and the second metal pattern layer comprises a Ti layer and an Al layer.

Growing community of inventors

Suwon, South Korea

Yeon-Hong Jee