Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Seoul National University

Postech Academy-industry Foundation

Yeon-Gon Cho

Soo-Jung Ryu

Woong Seo

Dong-Hoon Yoo

Bernhard Egger

John Dongjun Kim

Min-Seok Lee

Seok-Woo Song

Jae-Young Kim

Il-hyun Park

Moo-Kyoung Chung

Soo-jung Ryu

Hee-jun Shim

Sang-Heon Lee

Jin-Seok Lee

Chang-Moo Kim

Do-Hyun Kim

Jin-Hoo Lee

Ho-Young Kim

Won-Sub Kim

Jinseok Lee

Hee-Jin Ahn

Heejun Shim

Yeong-gil Shin

Sung-Joo Yoo

Yen-Jo Han

Seung-Hun Jin

Yenjo Han

Key-Young Choi

Byeong-Hun Lee

A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.

Processing device and a swizzle pattern generator

A graphics processing unit (GPU), configured to perform tile-based rendering using prefetched graphics data, includes a tiler configured to perform binning on a current frame and obtain a first binning bitstream of a first tile among a plurality of tiles of the current frame, a binning correlator configured to determine whether the first tile and a second tile of a previous frame are similar to each other by using the first binning bitstream and a second binning bitstream of the second tile, where the second tile has a same tile ID as the first tile, a prefetcher configured to prefetch second graphics data used to render the second tile by using the tile ID, when it is determined that the first tile and the second tile are similar to each other, and at least one processor configured to render the current frame using the prefetched second graphics data.

Apparatus and method for performing tile-based rendering using prefetched graphics data

A texture processing method and apparatus that obtains information about a first data loss amount that occurred during a texture compression process. A determination is made regarding a second data loss amount that allowable during a texture filtering process based on the obtained information regarding the first data loss amount. Texture filtering is then performed by using the second data loss amount. At least one processor determines the second data loss amount based on a difference between the third data loss amount and the first data loss amount.

Texture processing method and device

An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.

Job scheduling optimization based on ratio of stall to active cycles

A method of processing a graphics pipeline in a graphics processing apparatus includes performing pixel shading to process pixels corresponding to an object, texturing the object, and transmitting data of a textured object to a processing path for a post-processing operation of the textured object. A graphics processing apparatus for processing a graphics pipeline includes a shading processor configured to perform pixel shading to process pixels corresponding to an object. A texturing processor is configured apply to texture the object, determine a post-processing operation mode to adjust visual effects of the textured object, and transmit data of the textured object to a processing path for the post-processing operation in accordance with the determined post-processing mode. A reorder buffer is configured to buffer data of the object in accordance with a processing order when the processing path bypasses the shading processor.

Graphics processing apparatus and method of processing graphics pipeline thereof

Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.

Processor and method for dynamically allocating processing elements to front end units using a plurality of registers

A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the results of the processing in a register file based on the latency of each instruction.

Pipeline processor and an equal model compensator method and apparatus to store the processing result

A functional unit for supporting multithreading, a processor including the same, and an operating method of the processor are provided. The functional unit for supporting multithreading includes a plurality of input ports configured to receive opcodes and operands for a plurality of threads, wherein each of the plurality of input ports is configured to receive an opcode and an operand for a different thread, a plurality of operators configured to perform operations using the received operands, an operator selector configured to select, based on each opcode, an operator from among the plurality of operators to perform a specific operation using an operand from among the received operands, and a plurality of output ports configured to output operation results of operations for each thread.

Functional unit for supporting multithreading, processor comprising the same, and operating method thereof

Provided is a hardware debugging apparatus and method for a software-pipelined program. The hardware debugging apparatus and method overcome a currency problem caused during hardware debugging in the software-pipelined program by guarding certain execution blocks and restarting the processing of the software-pipelined program.

Hardware debugging apparatus and method for software pipelined program

A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores.

Multi-core apparatus and job scheduling method thereof

A coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof are provided to reduce a capacity of a configuration memory and reduce power consumption in a processor chip. The coarse-grained reconfigurable processor includes a configuration memory configured to store reconfiguration information including a header storing a compression mode indicator and a compressed code for each of a plurality of units and a body storing at least one uncompressed code, a decompressor configured to specify a code corresponding to each of the plurality of units among the at least one uncompressed code within the body based on the compression mode indicator and the compressed code within the header, and a reconfigurator including a plurality of PEs and configured to reconfigure data paths of the plurality of PEs based on the code corresponding to each unit.

Coarse-grained reconfigurable processor and code decompression method thereof

Provided is a reconfigurable processor that may process a first type of operation in first mode using a first group of functional units, and process a second type of operation in second mode using a second group of functional units. The reconfigurable processor may selectively supply power to either the first group or the second group, in response to a mode-switch signal or a mode-switch instruction.

Reconfigurable processor using power gating, compiler and compiling method thereof

A method of compiling a program to be executed on a multicore processor is provided. The method may include generating an initial solution by mapping a task to a source processing element (PE) and a destination PE, and selecting a communication scheme for transmission of the task from the source PE to the destination PE, approximately optimizing the mapping and communication scheme included in the initial solution, and scheduling the task, wherein the communication scheme is designated in a compiling process.

Growing community of inventors

Hwaseong-si, South Korea

Yeon-Gon Cho