Udmtek

Yeon Dong Kim

Nam Ki Kim

Seung Jong Jin

Yoon Woo Ha

Hee Chan Yang

Gi Nam Wang

Jun Pyo Park

The present disclosure discloses a master pattern generation method which is a major pattern in a repeated cycle by analyzing programmable logic controller (PLC) logic, and a method for training a model that may analyze an error of a cycle using the generated master pattern. The master pattern generation method and the training method for a cycle analysis model according to the present disclosure are different from the related art in that the methods are a technology of processing a machine control language (low-level language) that is difficult for humans to analyze and converting the machine control language into an analyzable language (high-level language), i.e., a machine language processing (MLP)-based technology that analyzes the executed machine language (a language that controls a machine) with a computer and can be understood by humans.

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Hwaseong-si, South Korea

Yeon Dong Kim