Intel Corporation

YenTing Chiu

Tahir Ghani

Oleg Golonzka

Mohit K Haran

Dax M Crum

Dan S Lavric

Orb Acton

Jitendra Kumar Jha

David J Towner

An integrated circuit structure comprises a first and second vertical arrangement of horizontal nanowires in a PMOS region and in an NMOS region. A first gate stack having a P-type conductive layer surrounds the first vertical arrangement of horizontal nanowires. A second gate stack surrounds the second vertical arrangement of horizontal nanowires. In one embodiment, the second gate stack has an N-type conductive layer, the P-type conductive layer is over the second gate stack, and an N-type conductive fill is between N-type conductive layer and the P-type conductive layer to provide same polarity metal filled gates. In another embodiment, the second gate stack has an N-type conductive layer comprising Titanium (Ti) and 'Nitrogen (N) having a low saturation thickness of 3-3.5 nm surrounding the nanowires, and the N-type conductive layer is covered by the P-type conductive layer.

Gate-all-around integrated circuit structures having uniform threshold voltages and tight gate endcap tolerances

Growing community of inventors

Portland, OR, United States of America

YenTing Chiu