Sj Semiconductor (jiangyin) Corporation

Other

Yenheng Chen

Chengchung Lin

Chengtar Wu

Jangshen Lin

Chihon Ho

Chentar Wu

Yayuan Xue

Mingchih Chen

Han Huang

Han Xu

Chenguang Yin

The present disclosure provides a wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method. The substrate includes a first wiring layer, conductive pillars, a molding layer, a second wiring layer and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer, the first metal wire layer is exposed from a top surface of the first dielectric layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each conductive pillar are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The molding layer molds the conductive pillars. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

Wafer-level ASIC 3D integrated substrate, packaging device and preparation method

The present disclosure provides an antenna packaging structure radiating electromagnetic waves in a horizontal direction parallel to the device plane and a method making the same. The method includes: providing a support substrate, and forming a separation layer; forming a rewiring layer on the separation layer; forming an antenna array layer on the rewiring layer, the antenna array layer is electrically connected to the metal wire layer; the antenna array layer includes a plurality of antennas which radiates e-m waves in a horizontal direction; each antennas comprises first metal sheets extending along a first direction and second metal sheets extending along a second direction, the first metal sheets are arranged with sheets in parallel and spaced by an sheet-to-sheet interval, second metal sheets are arranged with sheets in parallel and spaced by an sheet-to-sheet interval; forming a molding material layer, which molds the antenna array layer.

Packaging structure radiating electromagnetic waves in horizontal direction and method making the same

The present disclosure provides a chip packaging structure and a method for preparing the same. The packaging structure includes a glass substrate, metal connecting posts, a first packaging layer, a connection layer, semiconductor chips, a filler layer, a second packaging layer, a controlled collapse chip connection (C4) layer, a base substrate, and a heat sink housing. In the present disclosure, metal connecting posts are pre-formed in a glass substrate, so that the glass substrate serves as an intermediate conduction layer, and the semiconductor chips and the C4 layer are respectively formed at opposite ends of the metal connecting posts to perform electrical connections, so that the number of process steps for preparing the packaging structure is minimized and the manufacturing cost is reduced.

Packaging structure and method for preparing same

A wafer system-level three-dimensional fan-out packaging structure and a manufacturing method therefor. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and a second surface opposite to each other; forming a conductive connecting post on the second surface of the redistribution layer; bonding the patch element to the second surface of the redistribution layer; forming a plastic packaging layer on the second surface of the redistribution layer; thinning the plastic packaging layer; forming a plurality of solder bumps on a side of the plastic packaging layer that faces away from the redistribution layer; cutting the redistribution layer and the plastic packaging layer to obtain a number of first package structures; and bonding a second package layer to the first surface of the redistribution layer of one of the first package structures.

Wafer system-level three-dimensional fan-out three-dimensional fan-out packaging structure and manufacturing method thereof

The present disclosure provides a three-dimensional stacked fan-out packaging structure and a method making the same. The structure includes: a first semiconductor chip, a first packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, an underfill layer under the second semiconductor chip, and a second packaging material layer. The formed three-dimensional stacked fan-out packaging structure can package two sets of fan-out wafers in the three-dimensional direction. A single package stacked up after die-cutting has two sets of chips in the third-direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, the integration of the package is improved, and the package volume can shrink.

Three-dimensional stacked fan-out packaging structure and method making the same

The present disclosure provides an antenna packaging structure radiating e-m waves in a horizontal direction and a vertical direction and a method making the same. The method includes: providing a support substrate, forming a separation layer on a surface of the support substrate; forming a rewiring layer on the separation layer; forming an antenna array layer on the rewiring layer, the antenna array layer is electrically connected to the metal wire layer; the antenna array layer includes first antennas and second antennas arranged in an array respectively, radiating e-m waves in the horizontal direction and the vertical direction respectively; forming a molding material layer; removing the support substrate and the separation layer; forming solder ball bumps on a surface of the rewiring layer away from the antenna array layer, the solder ball bumps are electrically connected to the metal wire layer; disposing a chip on the solder ball bumps.

Packaging structure radiating electromagnetic wave in horizontal direction and vertical direction and method making the same

The present disclosure provides a double-layer stacked 3D fan-out packaging structure and a method making the structure. The structure includes: a first semiconductor chip, a packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, and an underfill layer under the second semiconductor chip. The formed double-layer stacked 3D fan-out packaging structure is capable to package two sets of fan-out wafers in the three-dimension. A single package stacked up after die-cutting has two sets of chips in the third direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, thus improving the package integration level and reducing the package volume.

Double-layer stacked 3D fan-out packaging structure and method making the same

The present invention provides a SiP structure and method for a light emitting diode (LED) chip. The packaging structure includes: a heat sink structure, a first chip, a first packaging layer, a second packaging layer, a rewiring layer, an LED chip, a printed circuit board (PCB), and a third packaging layer. In the present invention, chips with a plurality of functions, including the first chip, the LED chip, and the like, are integrated into one packaging structure through fan-out system-level packaging, to meet a plurality of different system functional requirements and improve the performance of the packaging system. By the rewiring layer, a metal connecting pillar, a metal lead wire, and the like, the first chip, the LED chip, and the PCB are electrically connected, to achieve a three-dimensional vertically stacked package thereby effectively reducing the area of a SiP and improving the integration of the packaging system.

System-level packaging structure and method for LED chip

A wafer system-level fan-out packaging structure and a manufacturing method. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and an opposite second surface; providing a patch element, and bonding the patch element to the second surface; providing a die having a bump disposed on a front side, and bonding the front side of the die to the second surface of the redistribution layer through the bump; and forming a plastic packaging layer on the second surface of the redistribution layer, where the plastic packaging layer covers the patch element, back side and side surfaces of the die. In the wafer system-level fan-out packaging structure and the manufacturing method of the present disclosure, the die and the patch element are packaged in a plastic packaging layer, and the die and the patch element are connected and let out by the redistribution layer.

Wafer system-level fan-out packaging structure and manufacturing method

The present disclosure provides a fan-out packaging structure and a method of fabricating the same. The fan-out packaging structure includes a redistribution layer, a passivation layer, a semiconductor chip, a first packaging layer, a groove, first metal bumps, second metal bumps, an adapter board, a stacked chip package, a passive element, and a filling layer. By means of the present disclosure, various chips performing different functions can be integrated into one packaging structure, thereby improving the integration level of the fan-out packaging structure. By means of the redistribution layer, the adapter board, and the first and second metal bumps, a three-dimensional vertically stacked packaging is achieved. As the result, in addition to improved integration level, the conduction paths in the packaging structure can be effectively shortened, thereby reducing power consumption, increasing the transmission speed, and increasing the data processing capacity.

Fan-out packaging structure and method

The present disclosure provides a fan-out packaging structure and a method for fabricating the fan-out packaging. The fan-out packaging structure includes a first redistribution layer, a second redistribution layer, metal connecting posts, a semiconductor chip, a first filling layer, a first packaging layer, a stacked chip package, a passive element, a second filling layer, a second packaging layer, and metal bumps. By means of the present disclosure, various chips having different functions can be integrated into one packaging structure, thereby improving the integration of the fan-out packaging structure. By means of the first redistribution layer, the second redistribution layer, and the metal connecting posts, a three-dimensional vertical stacked packaging is achieved. In this way, the integration level of the packaging structure can be effectively improved, and the conduction path can be significantly shortened, thereby reducing the power consumption, increasing the signal transmission speed, and increasing the data processing capacity.

The present disclosure provides a fan-out chip packaging structure and a method to fabricate the fan-out chip package. The fan-out chip packaging structure includes a first redistribution layer, a second redistribution layer, metal connecting posts, a semiconductor chip, a first packaging layer, a stacked chip package, a passive element, a filling layer, a metal bumps, and a second packaging layer. By means of the present disclosure, various chips having different functions can be integrated into one package structure, thereby improving the integration level of the fan-out packaging structure. By means of the first redistribution layer, the second redistribution layer, and the metal connecting posts, a three-dimensional vertically stacked package is achieved. In this way, the integration level of the packaging structure can be effectively improved, and the conduction path can be effectively shortened, thereby reducing power consumption, increasing the transmission speed, and increasing the data processing capacity.

The present disclosure provides a three-dimensional chip packaging structure and a method of making thereof. The structure includes: a plurality of chips stacked to form a staggered structure, each chip has one end hanging out from a lower chip and another end exposed out and connecting to a pad disposed on the chip, metal connecting pillars formed on the pads, a packaging layer disposed on the metal connecting pillars and the chips, a rewiring layer formed on the packaging layer, and a metal bump formed on the rewiring layer. The structure and method making it do not involve the Through-Silicon-Via (TSV) process, which is commonly used to achieve three-dimensional stacking of chips but is costly at the same time. Instead, the structure and method adopt pads and metal connecting pillars for electric connection. Also, the packaging structure does not necessitate a substrate for support, which reduces the package size.

Three-dimensional chip packaging structure and method thereof

The present disclosure provides a wafer-level chip scale packaging structure and a method for manufacturing the same. The method includes the following steps: 1) providing a first supporting substrate; 2) placing a first chip on the first supporting substrate, and forming a first packaging layer on the first chip; 3) separating the first chip and the surface of the first packaging layer in contact with the first chip from the first supporting substrate, and attaching the other surface of the first packaging layer to a second supporting substrate; 4) disposing a second packaging layer on the surface of the first packaging layer which is in contact with the first chip; 5) forming a rewiring layer on the second packing layer, the rewiring layer is electrically connected to the first chip; and 6) electrically connecting a second chip to the rewiring layer.

Wafer-level chip scale packaging structure having a rewiring layer and method for manufacturing the wafer-level chip scale packaging structure

The present disclosure provides a semiconductor structure with an antenna and a method making the same. The semiconductor structure has an antenna substrate with a first surface and a second surface opposite to the first surface; an antenna module disposed on the first surface of the antenna substrate; and a redistribution layer disposed on the second surface of the antenna substrate. The semiconductor structure with the antenna according to the present application provides the antenna module and the redistribution layer on two opposite surfaces of the antenna substrate, the material of the antenna substrate for supporting the antenna module can be selected according to actual needs, to provide more options. Signal loss can be reduced through the selection of the antenna substrate; the redistribution layer is provided on the surface of the antenna substrate for bonding the semiconductor chips.

Growing community of inventors

Jiangyin, China

Yenheng Chen