Mediatek Corporation

National Yang Ming Chiao Tung University

Yen-Yu Lin

Ting-Cheng Hsu

Chang-Fu Lin

Shih-Chang Hu

Chih-Wei Ko

Shiau-Wan Chen

Tyng-Luh Liu

A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO unit is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO unit. A virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. When the DMA unit reads data from or writes data into the virtual FIFO unit, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. A virtual port is electrically connected to the DMA unit and the processor. A processor reads data from or writes data into the virtual FIFO unit via the virtual port and the DMA unit.

Virtual first in first out (FIFO) direct memory access (DMA) device, electronic device and memory access method using the same

A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.

Processing modules with multilevel cache architecture

A memory system is described. A processor provides a data access address, and selectively configures a selected number of the ways of a memory device as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belonging to a directly addressable region by the memory configuration information stored in control registers. A cache hit detection circuit includes an address register storing the data access address, tag memories storing tag data of the data access address, a data processing device selectively outputting the tag data or an adjusted tag data as processed data according to a direct address signal, and address comparators each comparing the processed data with portion bits of the data access address from the address register, and outputting an address match signal as comparison match. The tag data is adjusted to a predetermined address by the data processing device, which is the highest address of memory space of the processor.

Memory access systems and methods for configuring ways as cache or directly addressable memory

The present invention discloses an object-detection method and a multi-class Bhattacharyya Boost algorithm used therein, wherein firstly, integral images are calculated from an image data in order to speed up the extraction of the characteristics of the objects; then, multiple rectangles of different sizes are scanned at different locations of the image data, and the multi-class Bhattacharyya Boost algorithm is used to detect multi-class objects. In the present invention, the detection framework can use only one single boosted cascade to determine the status and position of the object inside the image data. The simultaneous multi-class detection of the present invention can effectively overcome the detection difficulties resulting from the diversification of object appearances under different conditions. Therefore, the present invention can detect multiple objects simultaneously and can also detect one object having multiple classes of appearances, and further, the detection speed and the system robustness of the present invention are superior to those of the conventional technologies.

Object-detection method multi-class Bhattacharyya Boost algorithm used therein

A transmission circuit for realizing a rate adaptation layer of a digital communication system. The transmission circuit includes a processor and a format conversion circuit. The processor is capable of managing transmission rates of input and output digital signals of the digital communication system. The format conversion circuit includes a plurality of input units and output units; each input unit is for receiving a bit according to the input digital signal, and each output unit is for transmitting a bit to form the output signal. Each input unit and output unit are connected by hardware wires to realize data formatting such as bit-reordering, command insertion.

Transmission circuit for a digital communication system

A system clock switching apparatus, which includes a clock source for providing a reference clock signal; a frequency divider electrically connected to the clock source for dividing the reference clock signal to produce a frequency-divided signal and a system clock signal; and an enable signal generator electrically connected to the frequency divider for dividing the frequency-divided signal to produce at least one enable signal. The frequency divider switches the frequency of the system clock signal at a time period corresponding to a pulse edge of the frequency-divided signal.

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Taipei, Taiwan

Yen-Yu Lin